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document number: mc34708 rev. 8.0, 8/2012 freescale semiconductor ? advance information * this document contains certain information on a new product. ? specifications and information herein are subject to change without notice. ? freescale semiconductor, inc. , 2011-2012. all rights reserved. power management integrated circuit (pmic) for i.mx50/53 families the mc34708 is the power management integrated circuit (pmic) designed specifically for use with the freescale i.mx50 and i.mx53 families. features ? six multi-mode buck regulators for direct supply of the processor core, memory, and peripherals ? boost regulator for usb otg support ? eight regulators with internal and external pass devices for thermal budget optimization ? usb/uart/audio switching for mini-micro usb connector ? 10-bit adc for monitoring battery and other inputs ? real time clock and crystal oscill ator circuitry with coin cell backup/ charger ? spi/i 2 c bus for control and register interface figure 1. mc34708 simpli fied application diagram power management 34708 applications tablets smart mobile devices portable navigation devices vk suffix (pb-free) 206 mapbga 8.0 x 8.0 (0.5 mm pitch) vm suffix (pb-free) 206 mapbga 13.0 x 13.0 (0.8 mm pitch)

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analog integrated circuit device data ? freescale semiconductor 2 mc34708 table of contents 1 orderable parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 part identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.2 format and examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.3 fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 internal block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.1 simplified internal diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4 pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4.1 pinout diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4.2 pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5 general product characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.1 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.2 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.2.1 power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.3.2 general pmic specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.3.3 current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7 functional block descripti on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.1 startup requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.2 bias and references block description and application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.3 clocking and oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.3.1 clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.3.2 srtc support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.3.3 coin cell battery backup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.4 interrupt management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.4.1 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.4.2 interrupt bit summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7.5 power generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.5.1 power tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.5.2 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.5.3 power control logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.5.4 buck switching regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 7.5.5 boost switching regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 7.5.6 linear regulators (ldos) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 7.6 battery management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 7.7 analog to digital converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 7.7.1 input selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 7.7.2 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 7.7.3 dedicated readings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 7.7.4 touch screen interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 7.7.5 adc specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 7.8 auxiliary circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 7.8.1 general purpose i/os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 7.8.2 pwm outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 7.8.3 general purpose led drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 7.8.4 mini/micro usb switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
analog integrated circuit device data ? 3 freescale semiconductor mc34708 7.9 serial interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 7.9.1 spi interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 7.9.2 i2c interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 7.9.3 spi/i2c specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 7.10 configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 7.10.1 register set structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 7.10.2 specific registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 7.10.3 spi/i2c register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 7.10.4 spi register?s bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 8 typical applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 8.1 application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 8.2 bill of material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 8.3 mc34708 layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 8.3.1 general board recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 8.3.2 component placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 8.3.3 general routing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 8.3.4 parallel routing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 8.3.5 differential routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 8.3.6 switching regulator layout recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 8.4 thermal considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 8.4.1 rating data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 8.4.2 estimation of junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 9 package mechanical dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 9.1 206-pin mapbga (8 x 8), 0.5 mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 9.2 206-pin mapbga (13 x 13), 0.8 mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 10 reference section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 11 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
analog integrated circuit device data ? freescale semiconductor 4 mc34708 orderable parts 1 orderable parts this section describes the part numbers av ailable to be purchased along with their di fferences. valid orderable part numbers ar e provided on the web. to determine the order able part numbers for this device, go to http://www.freescale.com and perform a part number search for the following device numbers. table 1. orderable part variations part number (1) temperature (t a ) package mc34708vk -40 to 85 c 206 mapbga - 8.0 x 8.0 mm - 0.5 mm pitch mc34708vm 206 mapbga - 13 x 13 mm - 0.8 mm pitch notes 1. to order parts in tape & reel, add the r2 suffix to the part number.
analog integrated circuit device data ? 5 freescale semiconductor mc34708 part identification 2 part identification this section provides an explanation of the part numbers and their alpha numeric breakdown. 2.1 description part numbers for the chips have fields that identify the specific part configuration. you can use the values of these fields to determine the specific part you have received. 2.2 format and examples part numbers for a given device have the following format, followed by a device example: table 2 - part numbering - analog : mc tt xxx r v pp rr - MC34708VKR2 2.3 fields these tables list the possible values for each field in the part number (not a ll combinations are valid). table 2: part numbering - analog field description values mc product category ? mc- qualified standard ? pc- prototype device tt temperature range ? 33 = -40 c to > 105 c ? 34 = -40 c to ? 105 c ? 35 = -55 c to ? 125 c xxx product number ? assigned by marketing r revision ? (default blank) v variation ? (default blank) pp package identifier ? varies by package rr tape and reel indicator ? r2 = 13 inch reel hub size
analog integrated circuit device data ? freescale semiconductor 6 mc34708 internal block diagram 3 internal block diagram 3.1 simplified internal diagram figure 2. simplified internal block diagram bp resetb resetbmcu wdi switchers gndadc adin11 mux 10 bit gp adc int clk32k xtal1 xtal2 gndrtc licell gpio control gpiolv1 gpiolv2 rtc + calibration gndsw2 sw2fb sw2lx sw1in sw2in o/p drive ` gndsw1a sw1fb sw3in o/p drive gndsw3 sw3fb sw3lx gndswbst swbstfb swbstin swbstlx o/p drive pwron1 pums1 monitor timer o/p drive pll 32 khz crystal osc standby gpiolv3 to interrupt section die temp & thermal warning detection lcell switch enables & control spi result registers interrupt inputs gndctrl core control logic, timers, & interrupts 32 khz internal osc gpiolv4 chrgledr licell, uid, die temp, gpo4 adin10 clk32kmcu gndreg1 gndreg2 adin9 a/d result a/d control ictest 32 khz buffers output pin input pin bi-directional pin package pin legend spi interface + muxed i2c optional interface cs clk gndspi miso spi registers mosi shift register shift register spivcc to enables & control to trimmed circuits spi control logic trim-in-package startup sequencer decode trim? pumsx control logic li cell charger sw2 lp 1000 ma buck sw3 int mem 500 ma buck swbst 380 ma boost voltage / current sensing & translation mc34708 sw4 dual phase ddr 1000 ma buck vsrtc vpll vpll 50 ma pass fet spi control vbus vinusb vusb uid connector interface best of supply licell bp reference generation vcoredig gndcore vcore vcoreref v b u s / i d d e t e c t o r s , h o s t a u t o d e t e c t i o n u a r t s w i t c h e s a u d i o s w i t c h e s vusb regulator subsana1 subspwr1 subsref subsgnd subspwr2 subsana3 subsana2 subsldo vinpll pums2 pwron2 glbrst sw5in o/p drive gndsw5 sw5fb sw5lx sw5 i/o 1000 ma buck vusb2 350ma vdacdrv vdac vusb2 vusb2drv vdac 250ma gndachrg sw1alx dvs control cfp cfn battisnsccn chrgledg dm dp dplus dminus ovp spkr sw1pwgd sw2pgd pwm outputs pwm1 pwm2 spkl mic rxd txd gndsw1b o/p drive sw1blx sw4ain gndsw4a sw4afb o/p drive sw4alx sw4bin gndsw4b sw4bfb o/p drive sw4blx gndusb sw4cfg ledvdd vddlp vgen1 250ma vgen2drv vgen2 vgen2 250ma pass fet vgen1 pass fet vingen1 pums3 pums4 sdwnb digital core pretmr tricklesel chrgfb battisnsn battisnsp bp chrglx vbusvin auxvin gaux gbat bpsns gotg vaux general purpose led drivers sw1 dual phase gp 2000 ma buck sw1cfg valways sw1vsssns bptherm ntcref batt battisnsccp itric pums5 gpiovdd gndgpio gndref1 gndref2 gndref ldovdd pass fet gndchrg adin14/tsy1 adin15/tsy2 adin13/tsx2 tsref touch screen interface adin12/tsx1 vinrefddr vrefddr 10ma vrefddr vhalf clk32kvcc vsrtc input/battery monitoring
analog integrated circuit device data ? 7 freescale semiconductor mc34708 pin connections 4 pin connections 4.1 pinout diagram figure 3. top view ballmap 1234 5 6 78910111213 a tricklesel gndachrg batt cfp bp vbusvin chrglx gndchrg ledvdd licell pwm1 gpiovdd b auxvin auxvin pretmr bptherm cfn gbat vbusvin chrglx gndchrg chrgledg gpiolv1 gndgpio pums3 c auxvin auxvin subsana3 ntcref chrgfb bpsns vbusvin chrglx gndchrg pwm2 gpiolv3 pums1 gndsw2 d vaux gotg gaux sdwnb vbusvin chrglx gndchrg ictest gpiolv2 pums5 sw2lx e resetb gndctrl pwron2 int battisnsccn battisnsp itric subspwr1 chrgledr gpiolv0 sw2fb sw2in f miso gndspi mosi spivcc resetbmcu battisnsccp battisnsn subspwr1 subspw r1 gndref2 swbstin swbstin g clk cs vinusb rxd txd glbrst pwron1 subspwr1 sw2pwgd sw3fb gndswbst gndswbst h vbus vusb uid valways subsref subspwr1 mic subspwr1 subspwr1 clk32kmcu clk32kvcc swbstfb clk32k j dm spkr vcoredig vddlp standby tsy2 tsy1 subspwr1 subspw r1 vdacdrv vinpll vpll vsrtc k dp spkl vcore tsx1 adin10 adin9 subspwr1 subspw r1 vhalf vgen2 vdac gndreg1 l dplus gndcore gndusb wdi tsx2 adin11 subspwr1 gndref1 sw1vsssns sw1cfg vinrefddr gndreg2 vusb2 m dminus gndref sw4cfg sw5fb sw1fb sw1pwgd vgen1 n vcoreref gndadc gndadc gndadc sw5in sw 5lx gndsw5 sw1in sw1in subsana1 p tsref gndsw4a gndadc gndadc sw4bfb sw4afb sw5in sw5lx gndsw5 gndsw1a sw1alx sw1in sw1blx r sw4alx sw4ain sw4bin sw4blx gndsw4b sw5in sw 5lx gndsw5 gndsw1a sw1alx sw1in sw1blx no connect no ball rtc ground usb adc spi/i2c legend ldos switching regulators control logic mi sc
analog integrated circuit device data ? freescale semiconductor 8 mc34708 pin connections 4.2 pin definitions table 3. mc34708 pin definitions pin number pin name pin function definition charger (function no longer supported on mc34708) a7, b7, c7, d7 vbusvin nc charger not supported. no connect b1, b2, c1, c2 auxvin nc charger not supported. no connect d1 vaux nc charger not supported. no connect a8, b8, c8, d8 chrglx nc charger not supported. no connect c5 chrgfb i connect to batt pin d2 gotg nc charger not supported. no connect d3 gaux nc charger not supported. no connect c6 bpsns i bp sense point a6 bp i 1. application supply point 2. input supply to the ic core circuitry 3. application supply voltage sense b6 gbat o connect to gnd e8 itric nc charger not supported. no connect e7 battisnsp i battery current sensing point.(optional) if required, connect a 20mw sense resist or between battisnsp and battisnsn f7 battisnsn i battery current sensing point (optional) if required, connect a 20mw sense resist or between battisnsp and battisnsn a4 batt i 1. battery positive terminal 2. battery current sensing point 2 3. battery supply voltage sense f6 battisnsccp nc coulomb counter not supported. no connect e6 battisnsccn nc coulomb counter not supported. no connect a2 tricklesel nc charger not supported. no connect b3 pretmr nc charger not supported. no connect a5 cfp nc coulomb counter not supported. no connect b5 cfn nc coulomb counter not supported. no connect a10 ledvdd o led supply
analog integrated circuit device data ? 9 freescale semiconductor mc34708 pin connections e10 chrgledr i red led driver b10 chrgledg i green led driver a3 gndachrg gnd analog ground a9, b9, c9, d9 gndchrg gnd ground c4 ntcref nc charger not supported. no connect b4 bptherm nc charger not supported. no connect ic core k3 vcore o regulated supply for the ic analog core circuitry j3 vcoredig o regulated supply for the ic digital core circuitry h4 valways o best of supply between battery and charger input n1 vcoreref o main bandgap reference j4 vddlp o vddlp reference l2 gndcore gnd ground for the ic core circuitry m2 gndref gnd ground reference for the ic core circuitry switching regulators n11, n12, p12, r12 sw1in i sw1 input p11, r11 sw1alx o sw1a switch node connection m10 sw1fb i sw1 feedback p10, r10 gndsw1a gnd ground for sw1a l9 sw1vsssns gnd sw1 sense m11 sw1pwgd o powergood signal for sw1 p13, r13 sw1blx o sw1b switch node connection p14, r14 gndsw1b gnd ground for sw1b l10 sw1cfg i sw1a/b mode configuration e13, d14, d15 sw2in i sw2 input d13, d14, d15 sw2lx o sw2 switch node connection e12 sw2fb i sw2 feedback c13, c14, c15 gndsw2 gnd ground for sw2 g10 sw2pwgd o powergood signal for sw2 h14, h15 sw3in i sw3 input g14, g15 sw3lx o sw3 switch node connection g11 sw3fb i sw3 feedback f14, f15 gndsw3 gnd ground for sw3 table 3. mc34708 pin definitions (continued) pin number pin name pin function definition
analog integrated circuit device data ? freescale semiconductor 10 mc34708 pin connections f11 gndref2 gnd ground reference for switching regulators r3 sw4ain i sw4a input r2 sw4alx o sw4a switch node connection p6 sw4afb i sw4a feedback p2 gndsw4a gnd ground for sw4a r4 sw4bin i sw4b input r5 sw4blx o sw4b switch node connection p5 sw4bfb i sw4b feedback r6 gndsw4b gnd ground for sw4b m6 sw4cfg i sw4a/b mode configuration n7, p7, r7 sw5in i sw5 input n8, p8, r8 sw5lx o sw5 output m7 sw5fb i sw5 feedback n9, p9, r9 gndsw5 gnd ground for sw5 l8 gndref1 gnd ground reference for switching regulators f12, f13 swbstin i boost regulator bp supply j14, j15 swbstlx o swbst switch node connection h12 swbstfb i boost regulator feedback g12, g13 gndswbst gnd ground for boost regulator ldo regulators l11 vinrefddr i vrefddr input supply p15 vrefddr o vrefddr regulator output k10 vhalf o half supply reference for vrefddr j11 vinpll i vpll input supply j12 vpll o vpll regulator output j10 vdacdrv o drive output for vdac regulator using external pnp device k12 vdac o vdac regulator output l14 ldovdd i supply pin for vusb2, vdac, and vgen2 m14 vusb2drv i 1. vusb2 input using internal pmos fet o 2. drive output for vusb2 regulator using external pnp device l13 vusb2 o vusb2 regulator output n14 vingen1 i vgen1 input supply m13 vgen1 o vgen1 regulator output n15 vgen2drv i 1. vgen2 input using internal pmos fet o 2. drive output for vint regulator using external pnp device k11 vgen2 o vgen2 regulator output j13 vsrtc o output regulator for srtc module on processor table 3. mc34708 pin definitions (continued) pin number pin name pin function definition
analog integrated circuit device data ? 11 freescale semiconductor mc34708 pin connections k13 gndreg1 gnd ground for regulators 1 l12 gndreg2 gnd ground for regulators 2 a13 gpiovdd i supply for gpiolv pins e11 gpiolv0 i/o general purpose input/output 0 b11 gpiolv1 i/o general purpose input/output 1 d11 gpiolv2 i/o general purpose input/output 2 c11 gpiolv3 i/o general purpose input/output 3 a12 pwm1 o pwm output 1 c10 pwm2 o pwm output 2 b12 gndgpio - gpio ground control logic a11 licell i/o 1. coin cell supply input 2. coin cell charger output m15 xtal1 i 32.768 khz oscillator crystal connection 1 l15 xtal2 i 32.768 khz oscillator crystal connection 2 k14 gndrtc gnd ground for the rtc block h11 clk32kvcc i supply voltage for 32 k buffer h13 clk32k o 32 khz clock output for peripherals h10 clk32kmcu o 32 khz clock output for processor e1 resetb o reset output for peripherals f5 resetbmcu o reset output for processor l4 wdi i watchdog input j5 standby i standby input signal from processor e4 int o interrupt to processor g8 pwron1 i power on/off button connection 1 e3 pwron2 i power on/off button connection 2 g7 glbrst i global reset c12 pums1 i power up mode supply setting 1 b14 pums2 i power up mode supply setting 2 b13 pums3 i power up mode supply setting 3 a14 pums4 i power up mode supply setting 4 d12 pums5 i power up mode supply setting 5 d10 ictest i connect to ground for normal mode operation. e2 gndctrl gnd ground for control logic f4 spivcc i supply for spi bus g2 cs i primary spi select input g1 clk i primary spi clock input f3 mosi i primary spi write input table 3. mc34708 pin definitions (continued) pin number pin name pin function definition
analog integrated circuit device data ? freescale semiconductor 12 mc34708 pin connections f1 miso o primary spi read output d4 sdwnb o indication of imminent system shutdown f2 gndspi gnd ground for spi interface usb h3 uid i/o usb otg transceiver cable id l3 gndusb gnd usb ground k1 dp i/o usb data + j1 dm i/o usb data ? l1 dplus i/o processor d+ m1 dminus i/o processor d- g4 rxd o uart receive g5 txd i/o uart transmit h7 mic o mic output j2 spkr i speaker right k2 spkl i speaker left h1 vbus i/o usb transceiver cable interface vbus & otg supply output h2 vusb o usb transceiver regulator output g3 vinusb i input option for uvusb; tie to swbst at top level. a to d converter k7 adin9 i adc generic input channel 9 k6 adin10 i adc generic input channel 10, l6 adin11 i adc generic input channel 11 k4 tsx1/adin12 i touch screen interface x1 or adc generic input channel 12 l5 tsx2/adin13 i touch screen interface x2 or adc generic input channel 13 j7 tsy1/adin14 i touch screen interface y1 or adc generic input channel 14 j6 tsy2/adin15 i touch screen interface y2 or adc generic input channel 15 p1 tsref o touch screen reference n2, n3, n4, p3, p4 gndadc gnd ground for a to d circuitry thermal grounds h5 subsref gnd substrate ground connection for reference circuitry e9, e7, f9, l7, g9, h6, h8, h9, j8, j9, k8, k9 subspwr1 gnd substrate ground connection for power devices sw1, sw4, sw5 k15 subsldo gnd substrate ground connection for all ldos n13 subsana1 gnd substrate ground connection for anal og circuitry of sw1, sw4, sw5 b15 subsana2 gnd substrate ground connection for anal og circuitry of sw2, sw3, swbst c3 subsana3 gnd substrate ground connection fo r analog circuitry of charger table 3. mc34708 pin definitions (continued) pin number pin name pin function definition
analog integrated circuit device data ? 13 freescale semiconductor mc34708 general product characteristics 5 general product characteristics 5.1 maximum ratings table 4. maximum ratings all voltages are with respect to ground unless otherwise noted. exceeding these ratings may caus e a malfunction or permanent damage to the device. symbol description (rating) max. unit notes electrical ratings v batt , v bp , v licell input supply pins ? batt, bp, bpsns ?licell 4.8 4.8 v input sense pins ? chrgfb ? battisnsp, battisnsn 7.5 5.5 v led drivers pins ? chrgledr, chrgledg 7.5 v ic core reference ? vcoredig ? vcore, vcoreref, vddlp ? valways 1.5 3.6 7.5 v switching regulators pins ? swxin, swxlx, swbstfb ? swxfb, swxpwgd, swxcfg ?swbstlx 5.5 3.6 7.5 v ldo regulator pins ? vrefddr, vhalf ? vpll, vgen1, vingen1, vsrtc ? vinrefddr,vdac, vusb2, vgen2, ? vinpll, vdacdrv, ldovdd, vusb2drv, vgen2drv 1.5 2.5 3.6 5.5 v gpio pins ? gpiovdd, gpiolvx, pwmx 2.5 v control logic pins ?ictest ? xtal1, xtal2 ? clk32kvcc, clk32k, clk32kmcu, wdi, standby,int, pwron1, pwron2, glbrst, pumsx, spivcc, cs, clk, mosi, miso, sdwnb 1.8 2.5 3.6 v mini/micro usb interface pins ? vbus input sense pin ? vusb ? uid, dp, dm, dplus, dminus, rxd, txd, mic, spkr, spkl, vinusb 20 3.6 5.5 v adc interface pins ? adinx, tsx1/adin12, tsx2/adin13, tsy1/adin14, tsy2/adin15, tsref 4.8 v
analog integrated circuit device data ? freescale semiconductor 14 mc34708 general product characteristics 5.2 thermal characteristics v esd esd ratings ? human body model all pins ? charge device model all pins ? air gap discharge model for uid, vbus, dp, and dm pins ? human body model (hbm) for uid, vbus, dp, and dm pins ? 2000 ? 500 ? 15000 ? 8000 v (2) (2) (3) notes 2. esd testing is performed in accordance with the human body model (hbm) (c zap = 100 pf, r zap = 1500 ? ), and the charge device model (cdm), robotic (c zap = 4.0 pf). 3. need external esd protection diode array to meet iec1000-4-2 15000 v air gap discharge requirement. (czap= 150 pf, rzap=330 ohm). table 5. thermal ratings all voltages are with respect to ground unless otherwise noted. exceeding these ratings may caus e a malfunction or permanent damage to the device. symbol description (rating) min. max. unit notes thermal ratings t a ambient operating temperature range -40 85 c t j operating junction temperature range -40 125 c t st storage temperature range -65 150 c t pprt peak package reflow temperature during reflow - note 5 c (4) , (5) 8.0 x 8.0 mm, thermal resistance and package dissipation ratings r ja junction to ambient natural convection ? single layer board (1s) - 93 c/w (6) , (7) r jma junction to ambient natural convection ? four layer board (2s2p) - 53 c/w (6) , (8) r jma junction to ambient (@200 ft/min.) ? single layer board (1s) - 80 c/w (6) , (8) r jma junction to ambient (@200 ft/min.) ? four layer board (2s2p) - 49 c/w (6) , (8) r jb junction to board - 34 c/w (9) r jc junction to case - 25 c/w (10) jt junction to package top ? natural convection - 3.0 c/w (11) 13 x 13 mm, thermal resistance and package dissipation ratings r ja junction to ambient natural convection ? single layer board (1s) - 57 c/w (6) , (7) r jma junction to ambient natural convection ? four layer board (2s2p) - 36 c/w (6) , (7) , (8) table 4. maximum ratings (continued) all voltages are with respect to ground unless otherwise noted. exceeding these ratings may caus e a malfunction or permanent damage to the device. symbol description (rating) max. unit notes
analog integrated circuit device data ? 15 freescale semiconductor mc34708 general product characteristics r jma junction to ambient (@200 ft/min.) ? single layer board (1s) - 48 c/w (6) , (8) r jma junction to ambient (@200 ft/min.) ? four layer board (2s2p) - 32 c/w (6) , (8) r jb junction to board - 22 c/w (9) r jc junction to case - 15 c/w (10) jt junction to package top ? natural convection - 3.0 c/w (11) notes 4. pin soldering temperature limit is for 10 seconds maximum duration. not designed for immersion soldering. exceeding these lim its may cause a malfunction or permanent damage to the device. 5. freescale?s package reflow capability m eets pb-free requirements for jedec standard j-std-020c. for peak package reflow temperature and moisture sensitivity levels (msl), go to www.free scale.com, search by part number [e.g. remove prefixes/suffixe s and enter the core id to view all orderable parts (i.e. mc33xxxd enter 33xxx), and review parametrics. 6. junction temperature is a function of on-ch ip power dissipation, package thermal resi stance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of othe r components on the board, and board thermal resistance. 7. per jedec jesd51-2 with the single layer board horizontal. board meets jesd51-9 specification. 8. per jedec jesd51-6 with the board horizontal. 9. thermal resistance between the die and the printed circuit board per jedec jesd51-8. board temperature is measured on the top surface of the board near the package. 10. thermal resistance between the die and the case top surface as measured by the cold plate method (mil spec-883 method 1012.1 ). 11. thermal characterization parameter indicating the temperat ure difference between package top and the junction temperature pe r jedec jesd51-2. when greek letters are not available, the thermal characterization parameter is written as psi-jt. table 5. thermal ratings (continued) all voltages are with respect to ground unless otherwise noted. exceeding these ratings may caus e a malfunction or permanent damage to the device. symbol description (rating) min. max. unit notes
analog integrated circuit device data ? freescale semiconductor 16 mc34708 general product characteristics 5.2.1 power dissipation during operation, the temperature of the die should not exceed the maximum junction temperature. to optimize the thermal management scheme and avoid overheating, the mc34708 pm ic provides a thermal ma nagement system. the thermal protection is based on a circuit with a volt age output proportional to the absolute te mperature.this voltage can be read out vi a the adc for specific temperature readouts, see channel 3 die temperature . the aden spi bit must be set = 1 to enable the comparators for the thermal monitoring (therm110, therm120, therm125, therm130, and thermal shutdown). with aden = 0 the therma l monitors and thermal shutdown are disabled. interrupts therm110, therm120, therm125, and therm130 will be generated when respectively crossing in either direction the thresholds specified in table 6 . the temperature range can be determ ined by reading the thermxxxs bits. thermal protection is integrated to power of f the mc34708 pmic and disables the charger circuitry in case of over dissipation. this thermal protection will act above the maximum junction temp erature to avoid any unwanted power downs. the protection is debounced for 8.0 ms in order to suppress any (thermal) noise. this pr otection should be considered as a fail-safe mechanism and therefore the application design should be dimensioned such that this protection is not tripped under normal conditions. th e temperature thresholds and the sens e bit assignment are listed in table 6 . the therm1xx thresholds are debounced by the spi bits die_temp_db[1:0], which are programmable from 100 ? s to 4.0 ms (4.0 ms by default), see table 7 . when the die temperature crosses these thres holds, the corresponding sense bit will change and an interrupt will be generated to notify the soft ware that the hardware is reaching its thermal limit. table 6. thermal protection thresholds parameter min typ max units notes thermal 110 c threshold (therm110) 105 110 115 c thermal 120 c threshold (therm120) 115 120 125 c thermal 125 c threshold (therm125) 120 125 130 c thermal 130 c threshold (therm130) 125 130 135 c thermal warning hysteresis 2.0 - 4.0 c (12) thermal protection threshold 130 140 150 c notes 12. equivalent to approx. 30 mw min, 60 mw max table 7. die temp debounce settings die_temp_db [1:0] time units 00 0.100 ms 01 1.0 ms 10 2.5 ms 11 (default) 4.0 ms
analog integrated circuit device data ? 17 freescale semiconductor mc34708 general product characteristics 5.3 electrical characteristics 5.3.1 recommended operating conditions 5.3.2 general pmic specifications table 8. recommended operating conditions symbol description (rating) min. max. unit notes v bp main input supply 3.0 4.5 v v licell licell backup battery 1.8 3.6 v t a ambient temperature -40 85 c table 9. pin logic thresholds pin name internal termination (17) parameter load condition min max (20) unit notes pwron1, pwron2, glbrst pull-up input low 47 kohm 0.0 0.3 v (14) input high 1.0 mohm 1.0 vcoredig v (14) standby, wdi weak pull-down input low - 0.0 0.3 v (19) input high - 0.9 3.6 v (19) clk32k cmos output low -100 ? a 0.0 0.2 v output high 100 ? a clk32kvcc - 0.2 clk32kvcc v clk32kmcu cmos output low -100 ? a 0.0 0.2 v output high 100 ? a vsrtc - 0.2 vsrtc v resetb, resetbmcu, sdwnb, sw1pwgd, sw2pwgd open drain output low -2.0 ma 0.0 0.4 v (18) output high open drain - 3.6 v (18) gpiolv1,2,3,4 cmos input low - 0.0 0.3 * gpiovdd v input high - 0.7 * gpiovdd gpiovdd + 0.3 v output low - 0.0 0.2 v output high - gpiovdd - 0.2 gpiovdd v open drain output low -2.0 ma 0 0.4 v output high open drain - gpiovdd + 0.3 v pwm1, pwm2 cmos output low - 0.0 0.2 v output high - gpiovdd - 0.2 gpiovdd v clk, mosi input low - 0.0 0.3 * spivcc v (13) input high - 0.7 * spivcc spivcc + 0.3 v (13) cs weak pull-down input low - 0.0 0.4 v (13) input high - 1.1 spivcc + 0.3 v (13) cs, mosi (at booting for spi / i 2 c decoding) weak pull-down on cs input low - 0.0 0.3 * vcoredig v (13) , (21) input high - 0.7 * vcoredig vcoredig v (13) , (21)
analog integrated circuit device data ? freescale semiconductor 18 mc34708 general product characteristics miso, int cmos output low -100 ? a 0.0 0.2 v miso (13) (22) output high 100 ? a spivcc - 0.2 spivcc v miso (13) (22) pums1,2,3,4,5 input low pumsxs = 0 - 0.0 0.3 v (15) input high pumsxs = 1 - 1.0 vcoredig v (15) ictest input low - 0.0 0.3 v (16) input high - 1.1 1.7 v (16) sw1cfg, sw4cfg input low - 0.0 0.3 v input mid - 1.3 2.0 v input high - 2.5 3.1 v notes 13. spivcc is typically connected to the output of buck regulator sw5 and set to 1.800 v 14. input has internal pull-up to vcoredig equivalent to 200 kohm 15. input state is latched in first phase of cold start, refer to serial interfaces for a description of the pums configuration 16. input state is not latched 17. a weak pull-down represents a nominal internal pull-down of 100 na unless otherwise noted 18. resetb, resetbmcu, sdwnb, sw1pwgd, sw2pwgd have open drain outputs, external pull-ups are required 19. spivcc needs to remain enabled for proper detec tion of wdi high to avoid involuntary shutdown 20. the maximum should never exceed the ma ximum rating of the pin as given in pin connections 21. the weak pull-down on cs is disabled if a vih is detected at startup to avoid extra consumption in i 2 c mode 22. the output drive strength is programmable table 9. pin logic thresholds pin name internal termination (17) parameter load condition min max (20) unit notes
analog integrated circuit device data ? 19 freescale semiconductor mc34708 general product characteristics 5.3.3 current consumption the current consumption of the individual blocks is described in detail through out this specification. for convenience, a summa ry table follows for standard use cases. table 10. current consumption summary (25) characteristics noted under conditions bp = 3.6 v, v bus = 5.0 v, - 40 ? c ? t a ? 85 ? c, unless otherwise noted. typical values at bp = 3.6 v and t a = 25 c under nominal conditions, unless otherwise noted. mode description typ max unit notes rtc / power cut all blocks disabled, no main battery atta ched, coin cell is attached to licell ? (at 25 c only) ? rtc logic ? vcore module ?vsrtc ?32 k oscillator ? clk32kmcu buffer active(10 pf load) 4.0 8.0 ? a off (good battery) all blocks disabled, main battery attached * core and rtc module ?digital core ? rtc logic ?vsrtc ?32 k oscillator ? clk32kmcu buffer active (10 pf load) ? charger detect 20 55 ? a on standby low power mode (standby pin asserted and on_stby_lp=1) ?digital core ? rtc logic ? vcore module ?vsrtc ? clk32kmcu/clk32k active (10 pf load) ?32 k oscillator ?i ref ? sw1, sw2, sw3, sw4a, sw4b, sw5 in pfm (24) , (28) ? vddref, vpll, vgen1, vgen2, vusb2, vdac ? in low power mode (23) , (26) ?mini-usb 340 424 ? a on standby digital core ? rtc logic ? vcore module ?vsrtc ? clk32kmcu/clk32k active (10 pf load) ?32 k oscillator ?digital ?i ref ? sw1, sw2, sw3 sw4a, sw4b, sw5 in pfm (24) , (28) ? vddref, vpll, vgen1, vgen2, vusb2, vdac on ? in low power mode (24) , (26) ?mini-usb ? pll (for mini usb) 480 561 ? a
analog integrated circuit device data ? freescale semiconductor 20 mc34708 general product characteristics on typical use case ?digital core ? rtc logic ? vcore module ? vsrtc clk32kmcu/clk32k active (10 pf) ?32 k oscillator ?i ref ? sw1, sw2, sw3 sw4a, sw4b, sw5 in apskip swbst (24) , (27) , (28) ? vddref, vpll, vgen1, vgen2, vusb2, vdac on ? in low power mode (23) , (26) ?digital ?pll ?mini-usb 1600 3000 ? a notes 23. equivalent to approx. 30 mw min, 60 mw max 24. current in rtc mode is from licell=2.5 v; in all other modes from bp = 3.6 v. 25. external loads are not included (1) 26. vusb2, vgen2 external pass pnps 27. swbst in auto mode 28. sw4a output 2.5 v table 10. current consumption summary (25) characteristics noted under conditions bp = 3.6 v, v bus = 5.0 v, - 40 ? c ? t a ? 85 ? c, unless otherwise noted. typical values at bp = 3.6 v and t a = 25 c under nominal conditions, unless otherwise noted.
analog integrated circuit device data ? 21 freescale semiconductor mc34708 general description 6 general description 6.1 features power generation ? six buck switching regulators ? two single/dual phase buck regulators ? four single phase buck regulators ? pfm/auto pulse skip/pwm operation mode ? dynamic voltage scaling ?5 v boost regulator ? usb on-the-go support ? eight ldo regulators ? two with selectable internal or external pass devices ? five with embedded pass devices ? one with an external pnp device analog to digital converter ? seven general purpose channels ? internal dedicated channels ? resistive touchscreen interface auxiliary circuits ? mini/micro usb switch ? bidirectional audio/data/uart ? accessory identification circuit ? general purpose i/os ? pwm outputs ? two general purpose led drivers. clocking and oscillators ? real time clock ? time and day counters ? time of day alarm ? 32.768 khz crystal oscillator ? coin cell battery backup and charger serial interface ? spi ?i 2 c
analog integrated circuit device data ? freescale semiconductor 22 mc34708 general description 6.2 block diagram figure 4. functional block diagram 6.3 functional description the mc34708 power management integrated ci rcuit (pmic) represents a complete system power solution in a single package. designed specifically for use with the freescale i.mx50/53 fa milies. the mc34708 integrates six multi-mode buck regulators and eight ldo regulators for direct supply of the processor core, memory and peripherals. the usb switch enables the use of a single, mini or micro usb connector for usb, ua rt and audio connections, switching the relevant signals to the connector depending on the type of devic e connected. in addition, the mc34708 also integrates a real time clock, coin cell charger, a 13-channel 10-bit adc, 5 v usb boost regulator, two pwm output s, touch-screen in terface, status led drivers and four gpios. 10-bit adc core general purpose resistive touch screen interface 32.768 khz crystal oscillator real time clock srtc support with coin cell charger six buck regulators processor core split power domains ddr memory i/o eight ldo regulators peripherals 5 v boost regulator usb on the go supply mini/micro usb interface usb/uart/audio auto accessory detect bias & references trimmed bandgap general purpose i/o & pwm outputs dual led indicator power control logic state machine control interface spi/i 2 c mc34708
analog integrated circuit device data ? 23 freescale semiconductor mc34708 functional bloc k description 7 functional block description 7.1 startup requirements at power up, switching and linear regulators are sequentially enabled in time slots of 2.0 ms steps, to limit th e inrush current after an initial delay of 8.0 ms, in which the core circuitry gets enabled. to ens ure a proper power up sequence, the outputs of the switching regulators that are not enabled ar e discharged at the beginning of the cold start with weak pull downs on the output. for that same reason, a 8.0 ms delay allows the outputs of the linear regulator s to be fully discharged as well, through the built in discharge path. the peak inrush current per event is limit ed. any under-voltage detection at bp is masked while the power up sequencer is running. when the switching regulator is enabled it will start in pwm mode and for 3.0 ms and then it will switch over to the mode that it is programmed to in the spi. the power up mode select pins pumsx (x = 1,2,3,4,5) are used to conf igure the startup characterist ics of the regulators. supply enabling and output level options are sele cted by hardwiring the pumsx pins for the desired configuration. the recommended power up strategy for end products is to bring up as little of the system as possible at boot ing, essentially sequestering just the bare essentials to allow processor startup and software to run. with such a strategy, the startup transients are controlled at lower levels, and the rest of the system power tr ee can be brought up by software. this al lows optimization of supply ordering, where specific sequences may be required, as well as supply default values. software code can load up all of the required programmable options, to avoid sneak pat hs, under/over-voltage issues, startup surg es, etc, without any change in hardware. the state of the pumsx pins are latched in before any of the switching or linear regu lators are enabled, with the exception of vcore. pumsx options and start up configurations will be robust to a pcut event, whether occurring during normal operation or during the 8.0 ms of pre-sequencer initialization, i.e., the system will not end up in an unexpected / undesirable consumption state. table 11 shows the initial setup for the voltage level of the switching and linear regulators, and whether they get enabled. table 11. power up defaults i.mx reserved 53 lpm 53 ddr2 53 ddr3 53 lvddr3 53 lvddr2 50 50 50 50 50 50 pums[4:1] 0000-0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 pums5=0 vusb2 vgen2 reserved ext pnp ext pnp ext pnp ext pnp ext pnp ext pnp ext pnp ext pnp ext pnp ext pnp ext pnp pums5=1 vusb2 vgen2 reserved internal pmos internal pmos internal pmos internal pmos internal pmos internal pmos internal pmos internal pmos internal pmos internal pmos internal pmos sw1a (vddgp) reserved 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 sw1b (vddgp) reserved 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 sw2 (29) (vcc) reserved 1.225 1.3 1.3 1.3 1.3 1.2 1.2 1.2 1.2 1.2 1.2 sw3 (29) (vdda) reserved 1.2 1.3 1.2 1.2 1.2 1.2 1.2 1.2 1.2 1.2 1.2 sw4a (29) (ddr/sys) reserved 1.5 1.8 1.5 1.35 1.2 1.8 1.2 3.15 3.15 3.15 3.15 sw4b (29) (ddr/sys) reserved 1.5 1.8 1.5 1.35 1.2 1.8 1.2 1.2 1.8 1.2 1.8 sw5 (29) (i/o) reserved 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 swbst reserved off off off off off off off off off off off
analog integrated circuit device data ? freescale semiconductor 24 mc34708 functional block description the power up sequence is shown in tables 12 and 13 . vcoredig, vsrtc, and vcore, are brought up in the pre-sequencer startup. vusb (30) reserved 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 vusb2 reserved 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 vsrtc reserved 1.2 1.3 1.3 1.3 1.3 1.2 1.2 1.2 1.2 1.2 1.2 vpll reserved 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 vrefddr reserved on on on on on on on on on on on vdac reserved 2.775 2.775 2.775 2.775 2.775 2.5 2.5 2.5 2.5 2.5 2.5 vgen1 reserved 1.2 1.3 1.3 1.3 1.3 1.2 1.2 1.2 1.2 1.2 1.2 vgen2 reserved 2.5 2.5 2.5 2.5 2.5 3.1 3.1 3.1 3.1 2.5 2.5 notes 29. the swx node are activated in aps m ode when enabled by the startup sequencer. 30. vusb regulator is only enabled if 5.0 v is present on vbus. by default vusb will be supplied by vbus. swbst = 5.0 v powers up as does vusb, regardless of 5.0 v present on uvbus. by default vusb is supplied by swbst. table 12. power up sequence i.mx53 tap x 2.0 ms pums [4:1] = [0101,0110,0111,1000,1001] (i.mx53) 0 sw2 (vcc) 1 vpll (nvcc_ckih = 1.8 v) 2 vgen2 (vdd_reg= 2.5 v, external pnp 3 sw3 (vdda) 4 sw1a/b (vddgp) 5 sw4a/b, vrefddr (ddr/sys) 6 7 sw5 (i/o), vgen1 8 vusb (31) , vusb2 9 vdac notes: 31. the vusb regulator is only enabled if 5.0 v is present on the vbus pin. by default vusb will be suppl ied by the vbus pin. table 11. power up defaults i.mx reserved 53 lpm 53 ddr2 53 ddr3 53 lvddr3 53 lvddr2 50 50 50 50 50 50
analog integrated circuit device data ? 25 freescale semiconductor mc34708 functional bloc k description 7.2 bias and references block description and application information all regulators use the main bandgap as the reference. the main bandgap is bypassed with a capacitor at refcore. the bandgap and the rest of the core circuitry is supplied from vcor e. the performance of the regula tors is directly dependent on the performance of vcoredig and the bandgap. no external dc loading is allowed on vcoredig or refcore. vcoredig is kept powered as long as there is a valid supply and/or coin cell. table 14 shows the main characteristics of the core circuitry. table 13. power up sequence i.mx50 tap x 2.0 ms pums [4:1] = [0100, 1011, 1100, 1101, 1110, 1111] (i.mx50/i.mx53) 0 sw2 1 sw3 2 sw1a/b 3 vdac 4 sw4a/b, vrefddr 5 sw5 6 vgen2, vusb2 7 vpll 8 vgen1 9 vusb (32) notes: 32. the vusb regulator is only enabled if 5.0 v is present on the vbus pin. by default vusb will be supplied by the vbus pin. table 14. core voltages electrical specifications characteristics noted under conditions bp = 3.6 v, v bus = 5.0 v, - 40 ? c ? t a ? 85 ? c, unless otherwise noted. typical values at bp = 3.6 v and t a = 25 c under nominal conditions, unless otherwise noted. symbol characteristic min typ max unit notes vcoredig (digital core supply) v coredig output voltage ? on mode and off with good battery mode, and charging ? rtc mode - - 1.5 0.0 - - v (33) c coredig v coredig bypass capacitor - 1.0 - ? f vddlp (digital core supply - lower power) v ddlp output voltage ? on mode with good battery ? off mode with good battery ? rtc mode - - - 1.5 1.2 1.2 - - - v (34) c ddlp v ddlp bypass capacitor - 100 - pf (35) vcore (analog core supply) v core output voltage ? on mode and charging ? off and rtc mode - - 2.775 0.0 - - v (33) c core v core bypass capacitor - 1.0 - ? f
analog integrated circuit device data ? freescale semiconductor 26 mc34708 functional block description 7.3 clocking and oscillators 7.3.1 clock generation a system clock is generated for internal digital circuitry as well as for external applicati ons utilizing the clock output pins . a crystal oscillator is used for the 32.768 khz time base and generation of related derivative clocks. if the crystal o scillator is not running (for example, if the crystal is not present), an internal 32 khz oscillator will be used instead. support is also provided for an external secure real time clock (srtc) which may be integrated on a companion system processor ic. for media prot ection in compliance with digital rights management (drm) system requirements, the clk32kmcu can be provided as a reference to the sr tc module where tamper pr otection is implemented. 7.3.1.1 clocking scheme the internal 32 khz oscillator is an integrated backup for th e crystal oscillator, and provides a 32.768 khz nominal frequency at ? 60% accuracy, if running. the internal oscill ator only runs if a valid supply is availa ble at bp, and would not be used as long as the crystal oscillator is active. in absence of a valid supply at the bp supply node (for instance due to a dead battery), the crystal oscillator continues running supplied from the coin cell battery . all control functions will run off the crystal derived freque ncy, occasionally refe rred to as ?32 khz? for brevity?s sake. during the switch-over between the two clock sources (such as w hen the crystal oscillator is starting up), the output clock is maintained at a stable active low or high phase of the internal 32 khz clock to avoid any clocking glitches. if the xltal clock source suddenly disappears during operation, the ic will revert ba ck to the internal clock source. given the unpredictable natu re of the event and the startup times involved, the clock may be ab sent long enough for the application to shut down during this transition due to for instance a sag in the regulator output voltage or absence of a signal on the clock output pins. a status bit, clks, is available to indicate to the processor which clock is currently selected: clks = 0 when the internal rc is used and clks = 1 if the crystal source is used. the clki interrupt bit will be set whenever a change in the clock source occur s, and an interrupt will be generated if the corresponding clkm mask bit is cleared. 7.3.1.2 oscillator specifications the crystal oscillator has been optimized for use in conjunction with the micro crystal cc7v-t1a32.768 khz-9.0 pf-30 ppm or equivalent (such as micro crystal cc5v-t1a or epson fc135 ) and is capable of handling its parametric variations. the electrical characteristics of the 32 khz crystal oscillator are given in the following table, taking into account the crystal characteristics noted above. the oscillator accuracy depends largely on the temper ature characteristics of the used crystal. application circuits can be optimized for required accuracy by ad apting the external crystal osci llator network (via component accuracy and/or tuning). additionally, a clock calibration system is provided to adjust the 32,768 cycle counter that generates the 1.0 hz timer and rtc registers; see srtc support for more detail. vrefcore (bandgap / regulator reference) v refcore output voltage - 1.2 - v (33) absolute accuracy - 0.5 - % temperature drift - 0.25 - % c refcore v refcore bypass capacitor - 100 - nf notes 33. 3.0 v < bp < 4.5 v, no external loading on vcoredig, vddlp, vcore, or refcore. extended operation down to uvdet, but no system malfunction. 34. powered by vcoredig 35. maximum capacitance on v ddlp should not exceed 1000 pf, including the board capacitance. table 14. core voltages electrical specifications characteristics noted under conditions bp = 3.6 v, v bus = 5.0 v, - 40 ? c ? t a ? 85 ? c, unless otherwise noted. typical values at bp = 3.6 v and t a = 25 c under nominal conditions, unless otherwise noted. symbol characteristic min typ max unit notes
analog integrated circuit device data ? 27 freescale semiconductor mc34708 functional bloc k description 7.3.2 srtc support when configured for drm mode (spi bit drm = 1), the clk32kmcu driver will be kept enabled through all operational states to ensure that the srtc module always has its reference clock. if drm = 0, the clk32kmcu driver will not be maintained in the off state. it is also necessary to provide a means for the processor to do an rtc initiated wake-up of the system if it has been programme d for such capability. this can be accomplished by connecting an open drain nmos driver to the pwron pin of the mc34708 pmic, so that it is in effect, a parallel path for the power ke y. the mc34708 pmic will not be able to discern the turn on even t from a normal power key initiated turn on, but the processor sh ould have the knowledge, since the rtc initiated turn on is generated locally. table 15. oscillator and clock ma in electrical specifications characteristics noted under conditions bp = 3.6 v, v bus = 5.0 v, - 40 ? c ? t a ? 85 ? c, unless otherwise noted. typical values at bp = 3.6 v and t a = 25 c under nominal conditions, unless otherwise noted. symbol characteristic min typ max unit notes oscillator and clock output v inrtc operating voltage ? oscillator and rtc block from bp ? oscillator and rtc block from licell 1.8 1.8 - - 4.5 3.6 v i inrtc operating current crystal oscillator and rtc module ? all blocks disabled, no main batte ry attached, coin cell is attached to licell - 2.0 5.0 ? a t start-rtc rtc oscillator startup time ? upon application of power - - 1.0 sec v rtclo output low ? clk32k output sink 100 ? a ? clk32kmcu output source 50 ? a 0.0 - 0.2 v v rtchi output high ? clk32k output source 100 ? a ? clk32kmcu output sink 50 ? a clk32k vcc -0.2 vsrtc-0.2 - clk32k vcc vsrtc v t clk32ket clk32k rise and fall time, cl = 50 pf ? clk32kdrv [1:0] = 00 ? clk32kdrv [1:0] = 01 (default) ? clk32kdrv [1:0] = 10 ? clk32kdrv [1:0] = 11 - - - - 6.0 2.5 3.0 2.0 - - - - ns t ckl32k mcuet clk32kmcu rise and fall time ?cl = 12 pf - 22 - ns clk32k dc/ clk32k mcu dc clk32k and clk32kmcu output duty cycle ? crystal on xtal1, xtal2 pins 45 - 55 % rms output jitter ? 1 sigma for gaussian distribution - - 30 ns rms
analog integrated circuit device data ? freescale semiconductor 28 mc34708 functional block description figure 5. srtc block diagram 7.3.2.1 vsrtc the vsrtc regulator provides the clk32kmcu output level. additionally, it is used to bias the low power srtc domain of the srtc module integrated on certain fsl processors. the vsrtc regulator is enabled as soon as the rtcporb is detected. the vsrtc cannot be disabled. depending on the configuration of the pums[4:0] pi ns, the vsrtc voltage will be set to 1.3 or 1.2 v. with pums[4:0] = (0110, 0111, 1000, or 1001) vsrtc will be set to 1.3 v in on mode (on, on standby and on standby low power modes). in off and coin cell modes the vsrtc voltage will drop to 1.2 v with the pums[4:0] = (0110, 0111, 1000, or 1001). with pums[4:0] (0110, 0111, 1000, or 1001), vsrtc will be set to 1.2 v for all modes (on, on standby, on standby low power mode, off, and coincell). table 16. vsrtc electrical specifications characteristics noted under conditions bp = 3.6 v, v bus = 5.0 v, - 40 ? c ? t a ? 85 ? c, unless otherwise noted. typical values at bp = 3.6 v and t a = 25 c under nominal conditions, unless otherwise noted. symbol characteristic min typ max unit notes general v srtcin operating input voltage range v inmin to v inmax ? valid coin cell range ?valid bp 1.8 1.8 - - 3.6 4.5 v i srtc operating current load range il min to il max 0.0 - 50 ? a co srtc bypass capacitor value - 0.1 - ? f vsrtc - active mode - dc v srtc output voltage v out ?v inmin < v in < v inmax ?il min < il < il max ? off and coincell mode 1.15 1.20 1.28 v + + - - 34708 vcoredig pwronx spivcc=1.8 v gp domain=1.1 v lp dominant=1.2 v vsrtc=1.2 v ckil: vsrtc 0.1 ? f coin cell battery main battery clk32kmcu v srtc & detect on detect best of supply on/off button v coredig 32 khz open drain output for rtc wake-up processor i/o core supply sog supply srtc hp-rc lp-rtc 32 khz for dsm timing
analog integrated circuit device data ? 29 freescale semiconductor mc34708 functional bloc k description 7.3.2.2 real time clock a real time clock (rtc) is provided with time and day counter s as well as an alarm function. the rtc utilizes the 32.768 khz crystal oscillator for the time base and is powered by the coin cell backup supply when bp has dropped below operational range. in configurations where the srtc is used , the rtc can be disabled to conserve current drain by setting the rtcdis bit to a 1 (defaults on at power up). time and day counters the 32.768 khz clock is divided down to a 1.0 hz time tick which drives a 17 bit time of day (tod) counter. the tod counter counts the seconds during a 24 hour period from 0 to 86,399 and will then roll over to 0. when t he roll over occurs, it increme nts the 15 bit day counter. the day counter can count up to 32767 days. the 1.0 hz time tick can be used to generate a 1hzi interrupt if unmasked. time of day alarm a time of day alarm (toda) function can be used to turn on the application and alert the proce ssor. if the application is alrea dy on, the processor will be interrupted. the toda and daya regist ers are used to set the alarm time. when the tod counter is equal to the value in toda and the day counter is equal to the value in daya, the todai interrupt will be generated. timer reset as long as the supply at bp is valid, the real time clock will be supplied from vcoredig. if bp is not valid, the real time clo ck can be backed up from a coin cell via the licell pin. when the vsrtc voltage drops to the range of 0.9 - 0.8 v, the rtcporb reset signal is generated and the contents of the rtc will be re set. additional registers backed up by coin cell will also rese t with rtcporb. to inform the processor that the contents of the rtc are no longer valid due to the reset, a timer reset interrupt function is implemented with the rtcrsti bit. rtc timer calibration a clock calibration system is provided to adjust the 32,768 cycle counter that generates the 1.0 hz timer for rtc ti ming registers. the general implementation relies on the system processor to measure the 32.768 khz crystal oscillator against a higher frequency and more accurate system clock such as a tcxo. if the rtc timer needs a correction, a 5-bit 2?s complement calibration word can be sent via the spi to compensate the rtc for ina ccuracy in its reference oscillator. v srtc output voltage v out ?v inmin < v in < v inmax ?i lmin < i l < i lmax ? pums[4:0] ? (0110, 0111, 1000, 1001) ? on mode (on, standby, standby lpm) 1.15 1.2 1.25 v v srtc output voltage v out ?vinmin < v in < v inmax ?i lmin < i l < i lmax ? pums[4:0] = (0110, 0111, 1000, 1001) ? on mode (on, standby, standby lpm) 1.25 1.3 1.35 v i srtcq active mode quiescent current v inmin < v in < v inmax, il = 0 ? vsrtc = 1.2 v ? vsrtc = 1.3 v - - 1.7 2.7 - - ? a table 16. vsrtc elec trical specifications characteristics noted under conditions bp = 3.6 v, v bus = 5.0 v, - 40 ? c ? t a ? 85 ? c, unless otherwise noted. typical values at bp = 3.6 v and t a = 25 c under nominal conditions, unless otherwise noted. symbol characteristic min typ max unit notes
analog integrated circuit device data ? freescale semiconductor 30 mc34708 functional block description the available correction range should be sufficient to ensure drift accuracy in compliance with standards for drm time keeping. note that the 32.768 khz oscillator is not affected by rtccal settings; calibr ation is only applied to the rtc time base counter. therefore, the frequency at the cloc k output clk32k is not affected. the rtc system calibration is enabled by programming the rtccalmode[1:0] fo r desired behavior by operational mode. the rtc calibration circuitry can be automatically disabled when ma in battery contact is lost or if it is so deeply discharged that rtc power draw is switched to the coin cell (configured with rtccalmode=01). because of the low rtc consumption, rtc ac curacy can be maintained through long periods of the application being shut down, even after the main battery has discharged. however, it is not ed that the calibration can only be as good as the rtccal data that has been provided, so occasional refreshing is recommended to ensure that any drift infl uencing environmental factors have not skewed the clock beyond desired tolerances. 7.3.3 coin cell battery backup the licell pin provides a connection for a coin cell backup bat tery or supercap. if the main battery is deeply discharged, removed, or contact-bounced (i .e., during a power cut), the rt c system and coin cell maintained logic will switch over to the licell for backup power. this switch over occurs for a bp below 1.8 v threshold with licell greater than bp. a small capacitor should be placed from licell to ground under all circumstances. upon initial insertion of the coin cell, it is not immediatel y connected to the on chip circui try. the cell gets connected when the ic powers on, or after enabling the coin ce ll charger when the ic was already on. the coin cell charger circuit will function as a current-limited voltage source, result ing in the cc/cv taper characteristic ty pically used for rechargeable lithium-ion batteries. the coin cell char ger is enabled via the coinchen bit. the coin cell voltage is programmable through the vcoin[2:0] bits . the coin cell charger voltage is program mable in the on state where the charge current is fixed at icoinhi. if coinchen=1 when the system goes into of f or user off state, the coin cell charger will continue to charge to the predefined voltage setting but at a lower maximum current icoinlo. this co mpensates for self discharge of the coin cell and ensures that if/when the main cell gets depleted, that the coin cell will be topped off for maximum rtc retention. the coin cell charging wi ll be stopped for the bp below uvdet. the bit coinchen itself is only cleared when an rtcporb occurs. table 17. rtc calibration settings code in rtccal[4:0] correction in counts per 32768 relative correction in ppm 01111 +15 +458 00011 +3 +92 00001 +1 +31 00000 0 0 11111 -1 -31 11101 -3 -92 10001 -15 -458 10000 -16 -488 table 18. rtc calibration enabling rtccalmode function 00 rtc calibration disabled (default) 01 rtc calibration enabled in all modes except coin cell only 10 reserved for future use. do not use. 11 rtc calibration enabled in all modes
analog integrated circuit device data ? 31 freescale semiconductor mc34708 functional bloc k description 7.4 interrupt management 7.4.1 control the system is informed about important events, based on interr upts. unmasked interrupt events are signaled to the processor by driving the int pin high; this is true whether th e communication interface is configured for spi or i 2 c. each interrupt is latched so that even if the interrupt source becomes inactive, the interrupt will remain set until cleared. e ach interrupt can be cleared by writing a 1 to the appropriate bit in the interrupt status register, which will also cause the inte rrupt line to go low. if a new interrupt occurs while the processor clear s an existing interrupt bit, the interrupt line will remain high. each interrupt can be masked by setting the corresponding mask bit to a 1. as a result, when a masked interrupt bit goes high, the interrupt line will not go high. a masked interrupt can still be read from the interrupt status register. this gives the pr ocessor the option of polling for status from the ic. the ic powers up wi th all interrupts masked, so t he processor must initially poll the device to determine if any interrupts are ac tive. alternatively, the processor can unma sk the interrupt bits of interest. if a masked interrupt bit was already high, the interrupt line will go high after unmasking. the sense registers contain status and input sense bits, so the system processor can poll the cu rrent state of interrupt source s. they are read only, and not latched or clearable. interrupts generated by external events are debounced. therefore, the event needs to be stable throughout the debounce period before an interrupt is generated. nominal debounce periods for each event are documented in the int summary table following later in this section. due to the asynchronous nature of th e debounce timer, the effective d ebounce time can vary slightly. table 19. coin cell voltage specifications vcoin[2:0] output voltage 000 2.50 001 2.70 010 2.80 011 2.90 100 3.00 101 3.10 110 3.20 111 3.30 table 20. coin cell electrical specifications characteristics noted under conditions bp = 3.6 v, v bus = 5.0 v, - 40 ? c ? t a ? 85 ? c, unless otherwise noted. typical values at bp = 3.6 v and t a = 25 c under nominal conditions, unless otherwise noted. symbol characteristic min typ max unit notes coin cell charger v licellacc voltage accuracy - 100 - mv i licellon coin cell charge current in on and watchdog modes icoinhi - 60 - ? a i licelloff coin cell charge current in off, cold start/warm start, and low power off modes (user off / memory hold) icoinlo - 10 - ? a i licelacc current accuracy - 30 - % co licell licell bypass capacitor - 100 - nf licell bypass capacitor as coin cell replacement - 4.7 - ? f
analog integrated circuit device data ? freescale semiconductor 32 mc34708 functional block description 7.4.2 interrupt bit summary table 21 summarizes all interrupt, mask, and sens e bits associated with int control. for more detailed behavioral descriptions, refer to the related chapters. table 21. interrupt, mask and sense bits interrupt mask sense purpose trigger debounce time adcdonei adcdonem - adc has finished r equested conversions l2h 0 tsdonei tsdonem - touch screen has fi nished conversion l2h 0 tspendet tspendetm - touch screen pen detect dual 1.0 ms usbovp usbovpm usbovps vbus over-voltage sense is 1 if above threshold. dual programmable sup_ovp_db lowbatt lowbattm - low battery detect sense is 1 if below lowbat threshold h2l programmable vbattdb usbdet usbdetm usbdets usb vbus detect sense is 1 if detected dual programmable vbusdb stuck_key_rcv stuck_key_rcv_m - stuck key has recovered l2h stuck_key stuck_key_m - stuck key detected l2h adc_change adc_change_m adc_status adc result changed sense is 1 if conversion is completed, 0 if in progress l2h unknown_atta unknown_atta_m - unknown accessory detected l2h lkr lkr_m - remote control long key is released l2h lkp lkp_m - remote control long key is pressed l2h kp kp_m - remote control key is pressed l2h detach detach_m - accessory detached l2h attach attach_m - accessory attached l2h id_gnds sense is 1 if id pin is grounded id_floats sense is 1 if id pin is floating id_det_ends sense is 1 if id resistance detection is complete vbus_det_ends sense is 1 if vbus ptsi is complete scpi scpm - regulator short-circuit protection tripped l2h min. 4.0 ms max 8.0 ms 1hzi 1hzm - 1.0 hz time tick l2h 0 todai todam - time of day alarm l2h 0 pwron1i pwron1m pwron1s power on button 1 event sense is 1 if pwron1 is high h2l 30 ms (36) l2h 30 ms pwron2i pwron2m pwron2s power on button 2 event sense is 1 if pwron2 is high h2l 30 ms (36) l2h 30 ms sysrsti sysrstm - system reset through pwronx pins l2h 0 wdireseti wdiresetm - wdi silent system restart l2h 0 pci pcm - power cut event l2h 0
analog integrated circuit device data ? 33 freescale semiconductor mc34708 functional bloc k description warmi warmm warm start event l2h 0 memhldi memhldm memory hold event l2h 0 clki clkm clks 32 khz clock source change sense is 1 if source is xtal dual 0 rtcrsti rtcrstm - rtc reset has occurred l2h 0 therm110 therm110m therm110s thermal 110c threshold sense is 1 if above threshold dual programmable die_temp_db therm120 therm120m therm120s thermal 120c threshold sense is 1 if above threshold dual programmable die_temp_db therm125 therm125m therm125s thermal 125c threshold sense is 1 if above threshold dual programmable die_temp_db therm130 therm130m therm130s thermal 130c threshold sense is 1 if above threshold dual programmable die_temp_db gpiolvxi gpiolvxm gpiolvxs general purpose input interrupt programmable programmable notes 36. debounce timing for the falling edge can be extended with pwronxdbnc[1:0]; refer to turn on events for details. table 21. interrupt, mask and sense bits interrupt mask sense purpose trigger debounce time
analog integrated circuit device data ? freescale semiconductor 34 mc34708 functional block description 7.5 power generation the mc34708 pmic provides reference and supply voltages for the application processor as well as peripheral device. five buck (step down) converters and one b oost (step up) converters are included. one of the buck regulators can be configured in multiphase, single phase mode, or operate as separate ind ependent outputs (in this case, there are 6 buck converters). the buck converters provide the supply to processor cores and to ot her low voltage circuits such as io and memory. dynamic voltage scaling is provided to allow controlled supply rail adjustments fo r the processor cores and/or ot her circuitry. the boost conve rter provides power for the vbus in the otg mode, as well as the usb phy on the processor. the vusb regulator is powered from the boost to ensure sufficient headroom for the ldo th rough the normal discharge range of the main battery. linear regulators are directly supplied fr om the battery or from th e switching regulator, and include supplies for io and peripherals, such as audio, camera, bluetooth, wireless lan, etc. naming conventions are suggestive of typical or possible use case applications, but the switching and linear regulators may be utilized for othe r system power requirements within the guidelines of specified capabilities. four general purpose i/os ar e available, which can be conf igured as inputs/outputs. as in puts they can be configured as interrupts. 7.5.1 power tree refer to the representative tables and text specifying each su pply for information on performance metrics and operating ranges. table 22 summarizes the available power supplies. table 22. power tree summary supply purpose (typical application) output voltage (in v) load capability (in ma) sw1 buck regulator for processor vddgp domain 0.650 - 1.4375 2000 sw2 buck regulator for processor vcc domain 0.650 - 1.4375 1000 sw3 buck regulator for processor vdd domain and peripherals 0.650 - 1.425 500 sw4a buck regulator for ddr memory and peripherals 1.200 ? 1.85: 2.5/3.15 500 sw4b buck regulator for ddr memory and peripherals 1.200 ? 1.85: 2.5/3.15 500 sw5 buck regulator for i/o domain 1.200 ? 1.85 1000 swbst boost regulator for usb otg 5.00/5.05/5.10/5.15 380 vsrtc secure real time clock supply 1.2 0.05 vpll quiet analog supply 1.2/1.25/1.5/1.8 50 vrefddr ddr ref supply 0.6-0.9 10 vdac tv dac supply, external pnp 2.5/2.6/2.7/2.775 250 vusb2 vusb/peripherals supply, internal pmos 2.5/2.6/2.75/3.0 65 vusb/peripherals external pnp 2.5/2.6/2.75/3.0 350 vgen1 general peripherals supply #1 1.2/1.25/1.3/1.35/1.4/1.45/1.5/1.55 250 vgen2 general peripherals supply #2, internal pmos 2.5/2.7/2.8/2.9/3.0/3.1/3.15/3.3 50 general peripherals suppl y #2, external pnp 2.5/2.7/2.8/2.9/3.0/3.1/3.15/3.3 250 vusb usb transceiver supply 3.3 100
analog integrated circuit device data ? 35 freescale semiconductor mc34708 functional bloc k description 7.5.2 modes of operation the mc34708 pmic is fully programmable via the spi interfac e and associated register map. additional communication is provided by direct logic interfacing, including interrupt, watchd og, and reset. default startup of the device is selectable by hardwiring the power up mode select (pums) pins. power cycling of the application is driven by the mc34708 pmic . it has the interfaces for the power buttons and dedicated signaling interfacing with the processor. it also ensures the supp ly of the real time clock (rtc ), critical internal logic, and other circuits from the coin cell, in case of brief interruptions from the main battery. a charger for the coin cell is included to e nsure that it is kept topped off until needed. the mc34708 pmic provides the timekeeping, based on an integrated low power oscill ator running with a stand ard watch crystal. this oscillator is used for internal clocking, the control logic, and as a reference for the switcher pll. the timekeeping incl udes time of day, calendar, and alarm, and is backed up by coin ce ll. the clock is driven to the processor for reference and deep sl eep mode clocking. figure 6. power control state machine flow diagram off on user off memory hold warm start watchdog cold start user off wait internal memhold power cut from any mode: loss of power with pcen=0 thermal protection trip, or system reset unqual?d turn on wdi low, wdireset=0 unqual?d turn on turn on event pct[7:0] expired wdi low wdireset=1 and pcmaxcnt is exceeded wdi low wdireset=1 and pcmaxcnt is not exceeded start up modes reset timer expired reset timer expired watchdog timer expired turn on event (warm boot) turn on event (warm start) processor request for user off: useroffspi=1 pcut timeout pct[7:0] expired pcutexpb cleared to 0 low power off modes warm start enabled warm start not enabled warmen=1 warmen=0 application of power before pcut timer pct[7:0] expiration (pcen=1 and pcmaxcnt not exceeded) from any mode: loss of power with power cuts enabled (pcen=1) and pcmaxcnt not exceeded legend and notes (refer to text for additional details) blue box = steady state, no specific timer is running green circle = transitional state, a specific timer is running, see text dashed boxes = grouping of modes for clarification wdi has influence only in the ?on? state complete loss of bp and coin cell power is not represented in the state machine
analog integrated circuit device data ? freescale semiconductor 36 mc34708 functional block description the following are text descriptions of the power states of the system for additional details of the state machine to complement the drawing in figure 6 . note that the spi control is only possible in the watchdog, on and user off wait states and that the interrupt line int is kept low in all states except for watchdog and on. 7.5.2.1 coin cell the rtc module is powered from either the bat tery or the coincell, due to insufficient voltage at valways, and the ic is not in a power cut. no turn on event is accepted in the coin cell stat e. transition out (to the off state) requir es valways restoratio n with a threshold above uvdet. resetb an d resetbmcu are held low in this mode. the rtc module remains active (32 khz oscillator + rtc timers), along with valways level detection to qualify exit to the off state. vcoredig is off and the vddlp regulator is on, the rest of the system is put into it s lowest power configuration. if the coin cell is depleted (vstrc drops to 0.9 - 0.8 v while in the coin cell state), a complete system reset will occur. at next power application / turn on ev ent, the system will startup reinit ialized with all spi bits includi ng those that re set on rtcpor b restored to their default states. 7.5.2.2 off (with good battery) if the supply valways is above the uvdet threshold, only the ic core circuitry at vcoredig and the rtc module are powered, all other supplies are inactive. to ex it the off mode, a valid turn on event is required. no specific timer is running in this mode. resetb, resetbmcu are held low in this mode. if the supply valways is below the uvdet threshold, no turn on events are accepted. if a valid co in cell is present, the core gets powered from licell. the only active circuitry is t he rtc module and the detection vcore module powering vcoredig at 1.5 v. if there is a usb supply or charger inserted, the ic circui try at vcore, vcoredig, and the rtc module will be powered up. to exit the off mode, a valid turn on event is required. 7.5.2.3 cold start cold start is entered upon a turn on event from off, warm boot , successful pcut, or a silent system restart. the first 8.0 ms is used for initialization which includes bias generation, pu msx configuration latching, and qualification of the input supply level bp. the switching and linear regulators are then powered up sequent ially to limit the inrush current; see the power up section for sequencing and de fault level details. the reset sign als resetb and resetbmcu are kept low. the rese t timer starts running when entering cold start. the co ld start state is exited for the watchdog state and both resetb and resetbmcu become high (open drain output with extern al pull-ups) when the reset timer is expired. the input control pins wdi, and standby are ignored. 7.5.2.4 watchdog the system is fully powered and under spi control. rese tb and resetbmcu are high. the watchdog timer starts running when entering the watchdog st ate. when expired, the system transitions to the on state, where wdi will be checked and monitored. the input control pins wdi and standby are ignored while in the watchdog state. 7.5.2.5 on mode the system is fully powered and under spi control. resetb and resetbmcu are high. the wdi pin must be high to stay in this mode. the wdi io supply voltage is refe renced to spivcc (normally connected to sw5 = 1.8 v); spivcc must therefore remain enabled to allow fo r proper wdi detection. if wdi goes low, the system will transi tion to the off state or cold start (depending on the configuration; refer to the section on silent system restart with wdi ev ent for details). 7.5.2.6 user off wait the system is fully powered and und er spi control. the wdi pin no longer has co ntrol over the part. t he wait mode is entered by a processor request for user off by setting the useroffspi bit high. this is normally initiate d by the end user via the powe r key; upon receiving the correspon ding interrupt, the system will det ermine if the prod uct has been configured for user off or memory hold states (both of which first require passing through user off wait) or just transition to off.
analog integrated circuit device data ? 37 freescale semiconductor mc34708 functional bloc k description the wait timer starts running when entering user off wait mode. this leaves the processor time to suspend or terminate its task s. when expired, the wait mode is exited fo r user off mode or memory hold mode depending on warm starts being enabled or not via the warmen bit. the useroffspi bit is bein g reset at this point by resetb going low. 7.5.2.7 memory hold and user off (low power off states) as noted in the user off wait description, the system is directed into low power off states based on a spi command in response to an intentional turn off by the end user. the only exit then will be a turn on event. to an end user, the memory hold and use r off states look like the product has been shut down completely. however, a faster startup is fa cilitated by maintaining externa l memory in self-refresh mode (m emory hold and user off mode) as well as power ing portions of the processor core for state retention (user off only). the switching regulator mode control bits allow selective powering of the buck regulators for optimi zing the supply behavior in the low power off modes. linear regulators and most functional blocks are disabled (the rtc module, spi bits resetting with rtcporb, and turn on event detection are maintained). by way of example, the following descriptions assume the typica l use case where sw1 supplies the processor core(s), sw2 is applied to the processor?s vcc domain, sw3 supplies the proc essors internal memory/perip herals, and sw4 supplies the external memory, and sw5 supplies the i/o rail. the buck regulators are intended for direct connection to the aforementioned loads. 7.5.2.8 memory hold resetb and resetbmcu are low, and both clk32k and clk32kmcu are disabled (clk32km cu active if drm is set). to ensure that sw1, sw2, sw3, and sw5 shut off in memory hold, appropriate mode settings should be used such as sw1mhmode, = sw2mhmode, = sw3mhmode, = sw5mhmode set to = 0 (refer to the mode control description later in this section). since sw4 should be powered in pfm mode, sw4mhmode could be set to 1. upon a turn on event, the cold start state is entered, the de fault power up values are loaded, and the memhldi interrupt bit is set. a cold start out of the memory hold state will result in shorter boot times comp ared to starting out of the off state, sin ce software does not have to be loaded and expanded from flash. the st artup out of memory hold is also referred to as warm boot. no specific timer is running in this mode. buck regulators that are configured to stay on in memhold mo de by their swxmhmode settings will not be turned off when coming out of memhold and entering a warm boot. the switching r egulators will be reconfigured for their default settings as selected by the pumsx pins in the norma l time slot that would affect them. 7.5.2.9 user off resetb is low and resetbmcu is kept high. the 32 khz peripheral clock driver clk32k is disabled; clk32kmcu (connected to the processor?s ckil input) is maintained in this mode if the clk32kmcuen and useroffclk bits are both set, or if drm is set. the memory domain is held up by setting sw4uomode = 1. similarly, the sw1 and/or sw2 and or sw3 supply domains can be configured for swxuomode=1 to keep them powered through th e user off event. if one of the switching regulators can be shut down in user off, its mode bits would typically be set to 0. since power is maintained for the core (w hich is put into its lowest power state), and since m cu resetbmcu does not trip, the processor?s state may be quickly recovered when exiting us eroff upon a turn on event. the clk32kmcu clock can be used for very low frequency / low power idling of the core(s), minimi zing battery drain, while allowing a rapid recovery from where the system left off before the useroff command. upon a turn on event, warm start state is entered, and the defa ult power up values are loaded. a warm start out of user off will result in an almost instantaneous start up of the system, since the internal states of the processor were preserved along w ith external memory. no specific ti mer is running in this mode. 7.5.2.10 warm start entered upon a turn on event from user off. the first 8.0 ms is used for initialization, whic h includes bias generation, pumsx latching, and qualification of the input supply level bp. the sw itching and linear regulators are then powered up sequentially to limit the inrush current; see startup requirements for sequencing and default level details . if sw1, sw2, sw3, sw4, and/or sw5, were configured to stay on in user off mode by their swxuomode settings, t hey will not be turned off when coming out
analog integrated circuit device data ? freescale semiconductor 38 mc34708 functional block description of user off and entering a warm start. the buck regulators will be reconfigured for their default settings as selected by the pumsx pins in the respective time sl ot defined in the sequencer selection. resetb is kept low and resetbmcu is kept high. clk32kmcu is kept active if cl k32kmcu was set. the reset timer starts running when entering warm start. when expir ed, the warm start state is exited for the watchdog state, a warmi interrupt is generated, and resetb will go high. 7.5.2.11 internal memhold power cut as described in the power cut description , a momentary power interruption will put t he system into the inte rnal memhold power cut state if pcuts are enabled. the backup coin cell will now supply the mc34708 core, along with the 32 k crystal oscillator, the rtc system, and coin cell backed up registers. all regulators will be shut down to preserve the co in cell and rtc as long a s possible. both resetb and resetbmcu are tripped, bringing the entire system down, along with the supplies and external clock drivers, so the only recovery out of a power cut state is to reestablish power and initiate a cold start. if the pct timer expires before po wer is re-established, the system transitions to the off state and awaits a sufficient supply recovery. 7.5.3 power control logic 7.5.3.1 power cut description when the supply at valways drops below the uvdet threshold, due to batter y bounce or battery removal, the internal memhold power cut mode is entered and a power cut (pcut) ti mer starts running. the backup coin cell will now supply the rtc as well as the on chip memory registers and some other power control related bits. all other supplies will be disabled. the maximum duration of a power cut is determined by the pcut timer pct [7:0] preset via the spi. when a pcut occurs, the pcut timer will be started. the contents of pct [7:0] does not reflect the actual count do wn value, but will keep the programmed value, and therefore does not have to be reprogrammed after each power cut. if power is not re-established above the lo wbatt threshold before the pcut timer expires, the state machine transitions to the off mode at expiration of the counter, and clears the pcutexb bit by setting it to 0. this transition is referred to as an ?unsuccessful? pcut. in addition the pmic will bring the sdwnb pin low for one 32 khz clock cycle before powering down. upon re-application of power before expiration (a ?succe ssful pcut?, defined as valways first rising above the uvdet threshold and then battery above the lowbatt threshold before the pcut timer expires), a co ld start is engaged after the uvtimer has expired. in order to distinguish a non-pcut initiate d cold start from a cold start after a p cut, the pci interrupt should be checked by software. the pci interrupt is cleared by so ftware or when cycling through the off state. because the pcut system quickly disables the entire power tree, the battery voltage may recover to a level with the appearance of a valid supply once the battery is unloaded. however, upon a restart of the ic and power sequencer, the surge of current through the battery and trace impedances ca n once again cause the bp node to droop below uvdet. this chain of cyclic power down / power up sequences is referred to as ?ambulance mode?, and th e power control system include s strategies to minimize the chance of a product falling into and getting stuck in ambulance mode. first, the successful recovery out of a pcut requires the vabtt node to rise above lobatt thre shold, providing hysteretic margin from the lobattt (h to l) threshold. secondly, the number of times the pcut mode is entered is counted with the counter pccount [3:0], and the allowed count is limited to pcmaxcnt [3:0] set through spi. when the contents of both become equal, then the next pcut will not be supported and the system will go to of f mode, after the pcut time expires. after a successful power up after a pcut (i .e., valid power is reestablished, the syst em comes out of reset, and the processor reassumes control), softwa re should clear the pccount [3:0] counter. counting of pc ut events is enabled via the pccounten bit. this mode is only supported if the power cu t mode feature is enabled by setting the pcen bit. when not enabled, then in case of a power failure, the state machine will transition to the of f state. spi control is not possible durin g a pcut event and the interrupt line is kept low. spi configur ation for pcut support should also include setting the pcutexpb = 1 (see silent restart from pcut event ).
analog integrated circuit device data ? 39 freescale semiconductor mc34708 functional bloc k description 7.5.3.2 silent restart from pcut event if a short duration power cut event occurs (such as from a batte ry bounce, for example), it may be desirable to perform a silen t restart, so the system is reinitialized without alerti ng the user. this can be facilitated by setting the pcut expb bit to ?1? a t booting or after a cold start. this bit resets on rtcporb, therefore any subs equent cold start can first check the status of pcutexpb and the pci bit. the pcutexpb is cleared to ?0? when transitioning from pcut to off. if there was a pcut interrupt and pcutexpb is still ?1?, then the state machine has not transitione d through off, which confirms t hat the pct timer has not expir ed during the pcut event (i.e., a successful power cut). in this case, a silent restart may be appropriate. if pcutexpb is found to be ?0? after the cold start where pci is found to be ?1?, th en it is inferred that the pct timer has ex pired before power was reestablished, flagging an unsuccessful power cut or first power up, so the startup user greeting may be desirable for playback. 7.5.3.3 silent system restart with wdi event a mechanism is provided for recovery if the system software somehow gets into an abnormal state which requires a system reset, but it is desired to make the reset a silent event so as to ha ppen without end user awareness. the default response to wdi goin g low is for the state machine to transi tion to the off state (when wdireset = 0). however, if wdireset = 1, the state machine will go to cold start without passing through off mode (i.e., does not generate an offb signal). a wdireset event will generate a maskable wd ireseti interrupt and also increment th e pccount counter. this function is unrelated to pcuts, but it shares the p cut counter so that the number of silent system restarts can be limited by the programmable pcmaxcnt counter. when pcut support is used, the software should set the pcutexpb bit to ?1?. since th is bit resets with rtcporb, it will not be reset to ?0? if a wdi falls and the state machine goes straig ht to the cold start state. t herefore, upon a restart, software can discern a silent system re start if there is a wdir eseti interrupt and pcutexpb = 1. the application may then determine that an inconspicuous restart without fanfare may be more app ropriate than launching into the welcoming routine. a pcut event does not trip the wdireseti bit. note that the system response to wdi is gated by the watchdog ti mer?once the timer has expired, then the system will respond as programmed by wdireset as described above. 7.5.3.4 turn on events when in off mode, the circuit can be powered on via a turn on event. the turn on events are listed by the following. to indicat e to the processor what event caused the system to power on, an interrupt bit is asso ciated with each of the turn on events. masking the interrupts related to the turn on events will not prevent the part to turn on except for the time of day alarm. if the part was already on at the time of the turn on event, the interrupt is still generated. ? power button press: pwron1 or pwron2 pulled low with correspond ing interrupts and sense bits pwron1i, or pwron2i and pwron1s, or pwron2s. a power on/off button is connected from pwronx to ground. the pwronx can be hardware debounced through a pr ogrammable debouncer pwronxdbnc [1:0] to avoid a response upon a very short (i.e., unintentional) key press. bp should be above uvdet to allo w a power up. the pwronxi inte rrupt is generated for both the falling and the rising edge of the pwronx pin. by default, a 30 ms interrupt debounce is applied to both falling and rising edges. the falling edge debounce timing can be extended with pwronxdbnc[1:0] as defined in the following table. the pwronxi interrupt is cleared by softwa re or when cycling through the off mode. table 23. pwronx hardware debounce bit settings (37) bits state turn on debounce (ms) falling edge int debounce (ms) rising edge int debounce (ms) pwronxdbnc[1:0] 00 0.0 31.25 31.25 01 31.25 31.25 31.25 10 125 125 31.25 11 750 750 31.25 notes 37. the sense bit pwronxs is not debounced and follows the state of the pwronx pin.
analog integrated circuit device data ? freescale semiconductor 40 mc34708 functional block description ? battery attach: this occurs when bp crosses the lowbatt threshold whic h is equivalent to attaching a charged battery to the product. ? usb attach: vbus pulled high with corresponding interrupt and sense bi ts usbdet and usbdets. this is equivalent to plugging in a usb cable connected to a host powering the vbus line. the battery voltage sh ould be above lowbatt. for details on the usb detection, see mini/micro usb switch . ? rtc alarm: tod and day become equal to the alarm setting programm ed. this allows powering up a product at a preset time. bp should be above lowbatt. for details and related interrupts, see real time clock . ? system restart: system restart which may occu r after a system reset as descr ibed earlier in this sect ion. this is an optional function, see turn off events . bp should be above lowbatt. ? global system reset: the global reset feature powers down the part, disabl es the charger, resets the spi registers to their default value including all the rtcporb registers (except the drm bit, and the rtc registers), and then powers back on. to enable a global reset, the glbrst pin needs to be pulled low for greater than glbrsttmr [1:0] seconds and then pulled back high (defaults to 12 s). bp should be above lowbatt. 7.5.3.5 turn off events ? power button press (via wdi): user shutdown of a product is typically done by pressing the power button connected to the pwronx pin. this will generate an interrupt (pwronxi), but will not directly power off the part. the product is powered off by the processor?s response to this interrupt, which will be to pull wdi low. pressing the power button is therefore, under normal circumstances, not considered as a turn off event for th e state machine. however, since the button press power down is the most common turn off method for end products, it is de scribed in this section as the product implementation for a wdi initiated turn off event. note that the software can configure a user initiated power down, via a power button press for transition to a low power off mo de (memory hold or user off) for a quicker restart than t he default transition into the off sta te. ? power button system reset: a secondary application of the pwronx pins is the option to g enerate a system reset. this is recognized as a turn off event. by default, the system re set function is disabled but can be enabled by setting the pwronxrsten bits. when enabled, a four second long press on the power button will cause the device to go to the off mode, and as a result, the entire application will power down. an interrupt sysrsti is gener ated upon the next power up. alternatively, the system can be configured to rest art automatically by sett ing the restarten bit. ? thermal protection: if the die gets overheated, the thermal protection will power off the part to avoid damage. a turn on event will not be accepted while the thermal protection is still being tr ipped. the part will remain in off mode until cooling sufficiently to accept a turn on event. there are no specific interrupts related to this, other than the warning interrupts. ? bp lower than vbat_trkl: when the voltage at bp drops below vbat_t rkl[1:0] - 100mv, the state machine will transition to the off mode. the sdwnb pin is used to notify the processor that the pmic is going to immediately shutdown. the pmic will bring the sdwnb pin low for one 32 khz clock cycle before powering down. this signal will then be brought back high into the power off state. table 24. global reset time settings bits state time (s) glbrsttmr[1:0] 00 invalid 01 4 10 8 11 (default) 12 table 25. turn off voltage threshold vbat_trkl[1:0] turn off voltage threshold 00 2.8 01 2.9 10 3.0 (default) 11 3.1
analog integrated circuit device data ? 41 freescale semiconductor mc34708 functional bloc k description 7.5.3.6 timers the different timers as used by the state machine are listed by the following. this listing does not include rtc timers for timekeeping. a synchronization error of up to one clock peri od may occur with respect to the occurrence of an asynchronous event, the duration listed below is ther efore the effective minimum time period. 7.5.3.6.1 timing diagrams a turn on event timing diagrams shown in figure 7 . figure 7. power up timing diagram table 26. timer main characteristics timer duration clock under-voltage timer 4.0 ms 32 k/32 reset timer 40 ms 32 k/32 watchdog timer 128 ms 32 k/32 power cut timer programmable 0 to 8 seconds in 31.25 ms steps 32 k/1024 resetb wdi int uv masking 8 ms 20 ms 12 ms power up sequencer turn on verification 128 ms 2 - cold start 1 - off system core active 3 - watchdog 4 - on 1 - off 3- watchdog power up of the system upon a turn on event followed by a transition to the on state if wdi is pulled high ... or transition to off state if wdi remains low turn on event sequencer time slots wdi pulled low = indeterminate state ow turn on event is based on pwron being pulled low 8 ms
analog integrated circuit device data ? freescale semiconductor 42 mc34708 functional block description 7.5.3.7 power monitoring the voltage at batt and bp are monitor ed by detectors as summarized in table 27 . the uvdet and lowbatt thresholds are related to the power on/off events as described earlier in this chapter. the lowbatt threshold when transitioned from low to a high is used to power on the mc34708. the lowbatt threshold when transitioned from high to low, is used as a low battery detect warning. an interrupt lowbat is generated when dropping below the high to low threshold to indicate to the processor that the battery is weak and a shutdown is imminent. the lowbatt detection threshol d is debounced by the vbattd b[2:0] spi bi ts shown in table 28 . 7.5.3.8 power saving 7.5.3.8.1 system standby a product may be designed to go into dsm after periods of inac tivity, the standby pin is provided for board level control of timing in and out of such deep sleep modes. when a product is in dsm, it may be able to reduce the overal l platform current by lowering the regulator output voltage, chang ing the operating mode of the switching regulators or disabling some regulators. this can be obtained by controlling the standby pin. the configuration of the regulators in standby is pre-programmed through the spi. a lower power standby mode can be obtained by setting the on_stby_lp spi bit to a one. with the on_stby_lp spi bit set and the standby pin asserted a lower power standby will be entered. in the on standby low power mode, the switching regulators should all be programmed into pfm mode and th e ldo's should be configured to low power mode when the standby pin is asserted. the pll is disabled in this mode so the mini usb will only be able to detect if a charger is inserted. if an audio device, uart, or a usb otg device is attached the pmic will not be able to auto detect it in low power standby table 27. lowbatt detection thresholds threshold in v bit setting (38) uvdet (v) l to h transition (power on) (39) , (40) h to l transition (low battery detect) (39) , (40) lowbatt1 lowbatt0 lowbatt lowbatt 0 0 3.1 (rising) 2.65 (falling) 3.1 3.0 0 1 3.1 (rising) 2.65 (falling) 3.2 3.1 1 0 3.1 (rising) 2.65 (falling) 3.3 3.2 1 1 3.1 (rising) 2.65 (falling) 3.4 3.3 notes 38. default setting for lowbatt[1:0] is 11. 39. the above specified thresholds are 50 mv accurate for the indicated transition 40. a hysteresis is applied to the detectors on the order of 100 mv table 28. vbattdb debounce times vattdb[1:0] debounce time 00 0 (default) 01 2 rtc clock cycles 10 4 rtc clock cycles 11 8 rtc clock cycles
analog integrated circuit device data ? 43 freescale semiconductor mc34708 functional bloc k description mode. it will require the software to wake up occasionally to al low the mini-usb to detect if a device is attached by de-assert ing the standby pin and waking up for a period to see if a device is attached and then re-asserting standby, if a device has not been detected. if a device has been detected then the softwar e can bring up the appropriate application etc. note the standby pin is programmable for active high or active low polarity, and that decodin g of a standby event will take into account the programmed input polarity associated with each pin. for simplicity, standby will generally be referred to as a ctive high throughout this document, but as defined in table 29 , active low operation can be accommodated. finally, since standby pin activity is driven asynchronously to the system, a finite time is required for the internal logic to qualify and respond to the pin level changes. the state of the standby pin only has influence in on mode, and are therefore it is ignored duri ng start up and in the watchdog phase. this allows the system to power up without concern of the required standby polarities since software can make adjustments accordingly as soon as it is running. a command to transition to one of the low power off states (u ser off or memory hold, initiat ed with use-roffspi=1) redefines the power tree configuration based on swxmode programming, and ha s priority over standby (which also influences the power tree configuration). 7.5.3.8.2 standby delay a provision to delay the standby response is included. this al lows the processor and peripherals, some time after a standby instruction has been received, to terminate processes to fa cilitate seamless standby exiti ng and re-entrance into normal operating mode. a programmable delay is provided to hold off the system response to a standby event. when enabled (stbydly = 01, 10, or 11), stbydly will delay the standby initiated response for the entire ic until the stbydly counter expires. note that this delay is applied only when going into standby , and no delay is applied when coming out of standby. also, an allowance should be accounted for synchronization of the asynchronous standby event and the internal clocking edges (up to a full 32 k cycle of additional delay). table 29. standby pin and polarity control standby (pin) standbyinv (spi bit) standby control (41) 0 0 0 0 1 1 1 0 1 1 1 0 notes 41. standby = 0: system is not in standby standby = 1: system is in standby table 30. delay of standby- initiated response stbydly[1:0] function 00 no delay 01 one 32 k period (default) 10 two 32 k periods 11 three 32 k periods
analog integrated circuit device data ? freescale semiconductor 44 mc34708 functional block description 7.5.4 buck switching regulators six buck switching regulators are provided with integrated power switches and synchronous rectific ation. in a typical applicati on, sw1 and sw2 are used for supplying the application processo r core power domains. split power domains allow independent dvs control for processor power optimization, or to support te chnologies with a mix of device types with different voltage rati ngs. sw3 is used for powering internal processor memory as well as low voltage peripheral devices a nd interfaces which can run at the same voltage level. sw4a/b is used for powering extern al ddr memory as well as low voltage peripheral devices and interfaces, which can run at the same voltage level. sw5 is used to supply the i/o domain for the system. the buck regulators are supplied from the system supply bp, which is drawn from the main battery or the battery charger (when present). the switching regulators can operate in different modes depending on the load conditio ns. these modes can be set through the spi and include a pfm mode, pwm pulse skip, an automatic pulse skipping mode, and a pwm mode. the previous selection is optimized to maximum battery life based on load conditions. buck modes of operation are programmable for explicitly defined or load-dependent control. when initially activated, regulators output s will apply controlled stepping to the progr ammed value. the soft start feature lim its the inrush current at startup. during soft start, the regulator will be forced to pwm mode for 3.0 ms and then default to the aps mode a built in current limiter ensures that during normal operation the maximum current through the coil is not exceeded. point of load feedback is intended for minimi zing errors due to board level ir drops. 7.5.4.1 general control operational modes of the buck regulators can be controlled by direct spi programmi ng, altered by the state of the standby pin, by direct state machine influence (i.e., entering off or lo w power off states, for example), or by load current magnitude when so configured (auto pulse skip mode). available modes inclu de pwm with no pulse skipping (pwm), pwm with pulse skipping (pwmps), pulse frequency mode (pfm), automatic pulse skip ( aps), and off. the transition between the two modes pwmps and pwm can occur automatically, based on the load current (auto pulse skip mode). for light loading, the regulators should be put into pfm mode to optimize efficiency. sw1a/b, sw2, sw3, sw4a/b, and sw5, can be configured fo r mode switching with standby or autonomously, based on load current auto pulse skip mode. additionally, provisions are made for maintaining pfm operation in user off and memhold modes, to support state retention for faster star tup from the low power off modes for warm start or warm boot. swxmode[3:0] bits will be reset to their default values defined by pumsx settings by the startup sequencer. table 32 summarizes the buck regulators progra mmability for normal and standby modes. table 31. buck operating modes mode description off the regulator is switched off and t he output voltage is discharged pfm the regulator is switched on and set to pfm mode operation. in this mode, the regulator is always running in pfm mode. useful at light loads for optimized efficiency. pwmps the regulator is alternating between pul se skipping and pwm modes, depending on the load conditions. aps the regulator is switched on and set to au tomatic pulse skipping. in this mode the regulator moves automatically between pul se skipping and full pwm mode depending on load conditions. pwm the regulator is switched on and set to pwm m ode. in this mode the regulator is always in full pwm mode operation re gardless of load conditions. table 32. switching regulator mode control for normal and standby operation swxmode[3:0] normal mode standby mode 0000 off off 0001 pwm off
analog integrated circuit device data ? 45 freescale semiconductor mc34708 functional bloc k description in addition to controlling the operating m ode in standby, the voltage setting can be changed. the transition in voltage is hand led in a controlled slope manner, see dynamic voltage scaling for details. each regulator has an associated set of spi bits for standby mode set points. by default, the standby settings are i dentical to the non-standby sett ings which are initially defined by pumsx programming. the actual operating mode of the switching regulators as a functi on of the standby pin is not re flected through the spi. in oth er words, the spi will read back what is programmed in swxmode[3: 0], not the actual state that may be altered as described previously. two tables follow for mode control in t he low power off states. note that a low po wer off activated swx should use the standby set point as programmed by swxstby[4:0]. the activated regulato r(s) will maintain settings for mode and voltage until the next startup event. when the respective time slot of the startup se quencer is reached for a given regulator, its mode and voltage settings will be updated the same as if starting out of the of f state (except that switching re gulators active through a low po wer off mode will not be off when the startup sequencer is started). 0010 pwmps off 0011 pfm off 0100 aps off 0101 pwm pwm 0110 pwm aps 0111 off off 1000 aps aps 1001 pwm pwmps 1010 pwmps pwmps 1011 pwmps aps 1100 aps pfm 1101 pwm pfm 1110 pwmps pfm 1111 pfm pfm table 33. switching regulator control in memory hold swxmhmode memory hold operational mode (42) 0 off 1 pfm notes: 42. for memory hold mode, an activated swx should use the standby set point as programmed by swxstby[4:0]. table 34. switching regulator control in user off swxuomode user off operational mode (43) 0 off 1 pfm notes: 43. for user off mode, an activated swx should use the standby set point as programmed by swxstby[4:0]. table 32. switching regulator mode co ntrol for normal and standby operation swxmode[3:0] normal mode standby mode
analog integrated circuit device data ? freescale semiconductor 46 mc34708 functional block description in normal steady state operating mode, t he sw1xpwgd pin is high. when the buck charger set point is changed to a higher or lower set point, the sw1xpwgd pin will go low and will go high again when the higher/lower set point is reached. 7.5.4.2 switching frequency a pll generates the switching syst em clocking from the 32.768 khz crystal oscillator reference. the switching frequency can be programmed to 2.0 mhz or 4.0 mhz by setting the pllx spi bit as shown in table 35 . the clocking system provides a near instantaneous activation w hen the switching regulators ar e enabled or when exiting pfm operation for pwm mode. the pll can be conf igured for continuous operation with pllen = 1. 7.5.4.3 sw1 sw1 is fully integrated synchronous buck pwm voltage mode cont rol dc/dc regulator. it can be operated in single phase/dual phase mode. the operating mode of the switching regulators is configured by the sw1cfg pin. the sw1cfg pin is sampled at startup. table 35. buck regulator frequency pllx switching frequency (hz) 0 2 000 000 1 4 000 000 table 36. sw1 configuration sw1cfg sw1a/b configuration mode vcoredig single phase mode ground dual phase mode
analog integrated circuit device data ? 47 freescale semiconductor mc34708 functional bloc k description figure 8. sw1 single phase output mode block diagram figure 9. sw1 dual phase output mode block diagram driver contr oller sw1in sw 1alx sw1 fb i sen se c osw1a c in sw 1 a l sw 1a spi interface gndsw1a sw 1 sw1amode sw1 fault bp driver contr oller sw1 bin sw 1blx i sen se c in sw 1 b gndsw1b sw1bmode sw1 bfault bp sw 1cfg vcoredig ea z1 z2 internal com pensation v ref dac spi d sw 1 driver controller ea z1 z2 internal com pensation sw 1 in sw1 alx sw1 fb i sen se c osw1a c in sw 1 a l sw 1 a spi interface gndsw1a sw 1 sw1amode sw 1fault v ref dac spi bp driver controller sw 1bin sw1 blx i sen se c osw 1b c in sw 1 b l sw 1 b gndsw1b sw1bmode sw1bfault bp sw 1cfg d sw 1 a d sw 1b
analog integrated circuit device data ? freescale semiconductor 48 mc34708 functional block description the peak current is sensed internally fo r over-current protection purposes. if an ove r-current condition is detected the regula tor will limit the current through cycle by cycle operation and alert the syst em through the sw1fault spi bit and issue an scpi interrupt via the int pin. sw1a/b output voltage is spi conf igurable in step sizes of 12.5 mv as shown in the table below. the spi bits sw1a[5:0] set the output voltage for both the sw1a and sw1b. table 37. sw1a/b output voltage programmability set point sw1a[5:0] sw1a/b output (v) set point sw1a[5:0] sw1a/b output (v) 0 000000 0.6500 32 100000 1.0500 1 000001 0.6625 33 100001 1.0625 2 000010 0.6750 34 100010 1.0750 3 000011 0.6875 35 100011 1.0875 4 000100 0.7000 36 100100 1.1000 5 000101 0.7125 37 100101 1.1125 6 000110 0.7250 38 100110 1.1250 7 000111 0.7375 39 100111 1.1375 8 001000 0.7500 40 101000 1.1500 9 001001 0.7625 41 101001 1.1625 10 001010 0.7750 42 101010 1.1750 11 001011 0.7875 43 101011 1.1875 12 001100 0.8000 44 101100 1.2000 13 001101 0.8125 45 101101 1.2125 14 001110 0.8250 46 101110 1.2250 15 001111 0.8375 47 101111 1.2375 16 010000 0.8500 48 110000 1.2500 17 010001 0.8625 49 110001 1.2625 18 010010 0.8750 50 110010 1.2750 19 010011 0.8875 51 110011 1.2875 20 010100 0.9000 52 110100 1.3000 21 010101 0.9125 53 110101 1.3125 22 010110 0.9250 54 110110 1.3250 23 010111 0.9375 55 110111 1.3375 24 011000 0.9500 56 111000 1.3500 25 011001 0.9625 57 111001 1.3625 26 011010 0.9750 58 111010 1.3750 27 011011 0.9875 59 111011 1.3875 28 011100 1.0000 60 111100 1.4000 29 011101 1.0125 61 111101 1.4125 30 011110 1.0250 62 111110 1.4250 31 011111 1.0375 63 111111 1.4375
analog integrated circuit device data ? 49 freescale semiconductor mc34708 functional bloc k description table 38. sw1a/b electrical specification characteristics noted under conditions bp = 3.6 v, v bus = 5.0 v, - 40 ? c ? t a ? 85 ? c, unless otherwise noted. typical values at bp = 3.6 v and t a = 25 c under nominal conditions, unless otherwise noted. symbol characteristic min typ max unit notes sw1a/b buck regulator v sw1in operating input voltage ? pwm operation, 0 < il < i max ? pfm operation, 0 < il < il max 3.0 2.8 - - 4.5 4.5 v v sw1acc output voltage accuracy ? pwm mode including ripple, lo ad regulation, and transients ? pfm mode, including ripple, load regulation, and transients nom-25 nom-25 nom nom nom+25 nom+25 mv (44) i sw1 continuous output load current, v inmin < bp < 4.5 v ? pwm mode single/dual phase (parallel) ? sw1 in pfm mode - - - 50 2000 - ma i sw1peak current limiter peak current detection ?v in = 3.6 v, current through inductor - 4.0 - a i sw1 transient transient load change ? 100 ma/s - - 1.0 a v sw1os- start start-up overshoot, il = 0 - 25 mv t on-sw1 turn-on time ? enable to 90% of end value il = 0 - - 500 s f sw1 switching frequency ? pllx = 0 ? pllx = 1 - - 2.0 4.0 - - mhz i sw1q quiescent current consumption ? pwmps or aps mode, il=0 ma ? pfm mode, il=0 ma - - 240 15 - - a ? sw1 efficiency, ?pfm, 0.9 v, 1.0 ma ? pwm pulse skipping, 1.1 v, 200 ma ? pwm pulse skipping, 1.1 v, 800 ma ?pwm, 1.1 v, 1600 ma - - - - 54 75 81 76 - - - - % (45) notes: 44. transient loading for load steps of ilmax/2. 45. efficiency numbers at v in = 3.6 v, excludes the quiescent current
analog integrated circuit device data ? freescale semiconductor 50 mc34708 functional block description 7.5.4.4 sw2 sw2 is fully integrated synchronous buck pwm voltage-mode control dc/dc regulator. figure 10. sw2 block diagram the peak current is sensed internally for ov er-current protection purposes. if an ove r-current condition is detected, the regul ator will limit the current through cycle by cycle operation, alert th e system through the sw2fault spi bit, and issue an scpi interrupt via the int pin sw2 can be programmed in step sizes of 12.5 mv as shown in table 39 . table 39. sw2 output voltage programmability set point sw2[5:0] sw2x output (v) set point sw2[5:0] sw2 output (v) 0 000000 0.6500 32 100000 1.0500 1 000001 0.6625 33 100001 1.0625 2 000010 0.6750 34 100010 1.0750 3 000011 0.6875 35 100011 1.0875 4 000100 0.7000 36 100100 1.1000 5 000101 0.7125 37 100101 1.1125 6 000110 0.7250 38 100110 1.1250 7 000111 0.7375 39 100111 1.1375 8 001000 0.7500 40 101000 1.1500 9 001001 0.7625 41 101001 1.1625 10 001010 0.7750 42 101010 1.1750 11 001011 0.7875 43 101011 1.1875 12 001100 0.8000 44 101100 1.2000 13 001101 0.8125 45 101101 1.2125 14 001110 0.8250 46 101110 1.2250 15 001111 0.8375 47 101111 1.2375 16 010000 0.8500 48 110000 1.2500 driver controller ea z1 z2 internal compensation sw 2 in sw 2lx sw2 fb i sen se c osw2 c in sw 3 l sw 2 spi interface gndsw2 sw 2 sw 2mode sw2fault v ref dac spi bp d sw 2
analog integrated circuit device data ? 51 freescale semiconductor mc34708 functional bloc k description 17 010001 0.8625 49 110001 1.2625 18 010010 0.8750 50 110010 1.2750 19 010011 0.8875 51 110011 1.2875 20 010100 0.9000 52 110100 1.3000 21 010101 0.9125 53 110101 1.3125 22 010110 0.9250 54 110110 1.3250 23 010111 0.9375 55 110111 1.3375 24 011000 0.9500 56 111000 1.3500 25 011001 0.9625 57 111001 1.3625 26 011010 0.9750 58 111010 1.3750 27 011011 0.9875 59 111011 1.3875 28 011100 1.0000 60 111100 1.4000 29 011101 1.0125 61 111101 1.4125 30 011110 1.0250 62 111110 1.4250 31 011111 1.0375 63 111111 1.4375 table 40. sw2 electrical specifications characteristics noted under conditions bp = 3.6 v, v bus = 5.0 v, - 40 ? c ? t a ? 85 ? c, unless otherwise noted. typical values at bp = 3.6 v and t a = 25 c under nominal conditions, unless otherwise noted. symbol characteristic min typ max unit notes sw2 buck regulator v sw2in operating input voltage ? pwm operation, 0 < il < i max ? pfm operation, 0 < il < il max 3.0 2.8 - - 4.5 4.5 v v sw2acc output voltage accuracy ? pwm mode including ripple, lo ad regulation, and transients ? pfm mode, including ripple, load regulation, and transients nom-25 nom-25 nom nom nom+25 nom+25 mv (46) i sw2 continuous output load current, v inmin < bp < 4.65 v ? pwm mode ? pfm mode - - - 50 1000 - ma i sw2peak current limiter peak current detection ?v in = 3.6 v current through inductor - 2.0 - a i sw2 transient transient load change ? 100 ma/s - - 0.500 a v sw2os- start start-up overshoot, il = 0 - - 25 mv t on-sw2 turn-on time ? enable to 90% of end value il = 0 - - 500 s table 39. sw2 output voltage programmability set point sw2[5:0] sw2x output (v) set point sw2[5:0] sw2 output (v)
analog integrated circuit device data ? freescale semiconductor 52 mc34708 functional block description f sw2 switching frequency ? pllx = 0 ? pllx = 1 - - 2.0 4.0 - - - mhz i sw2q quiescent current consumption ? pwmps or aps mode, il = 0 ma; device not switching ? pfm mode, il = 0 ma; device not switching - - 160 15 - - a ? sw2 efficiency ?pfm, 0.9 v, 1.0 ma ? pwm pulse skipping, 1.2 v, 120 ma ? pwm pulse skipping, 1.2 v, 500 ma ?pwm, 1.2 v, 1000 ma - - - - 54 75 83 78 - - - - % (47) notes: 46. transient loading for load steps of ilmax/2. 47. efficiency numbers at v in = 3.6 v, excludes the quiescent current. table 40. sw2 electrical specifications characteristics noted under conditions bp = 3.6 v, v bus = 5.0 v, - 40 ? c ? t a ? 85 ? c, unless otherwise noted. typical values at bp = 3.6 v and t a = 25 c under nominal conditions, unless otherwise noted. symbol characteristic min typ max unit notes
analog integrated circuit device data ? 53 freescale semiconductor mc34708 functional bloc k description 7.5.4.5 sw3 sw3 is fully integrated synchronous buck pwm voltage mode control dc/dc regulator. figure 11. sw3 block diagram the peak current is sensed internally fo r over-current protection purposes. if an ove r-current condition is detected the regula tor will limit the current through cycle by cycle operation and alert the syst em through the sw3fault spi bit and issue an scpi interrupt via the int pin. sw3 can be programmed in step sizes of 25 mv as shown in table 41 . table 41. sw3 output voltage programmability set point sw3[4:0] sw3 output (v) set point sw3[4:0] sw3 output (v) 0 00000 0.6500 16 10000 1.0500 1 00001 0.6750 17 10001 1.0750 2 00010 0.7000 18 10010 1.1000 3 00011 0.7250 19 10011 1.1250 4 00100 0.7500 20 10100 1.1500 5 00101 0.7750 21 10101 1.1750 6 00110 0.8000 22 10110 1.2000 7 00111 0.8250 23 10111 1.2250 8 01000 0.8500 24 11000 1.2500 9 01001 0.8750 25 11001 1.2750 10 01010 0.9000 26 11010 1.3000 11 01011 0.9250 27 11011 1.3250 12 01100 0.9500 28 11100 1.3500 13 01101 0.9750 29 11101 1.3750 14 01110 1.0000 30 11110 1.4000 15 01111 1.0250 31 11111 1.4250 driver contr oller ea z1 z2 internal compensation sw3 in sw3lx sw 3 fb i sen se c osw3 c in sw 3 l sw 3 spi interface gndsw3 sw 3 sw3mode sw 3fault v ref dac spi bp d sw 3
analog integrated circuit device data ? freescale semiconductor 54 mc34708 functional block description table 42. sw3 electrical specification characteristics noted under conditions bp = 3.6 v, v bus = 5.0 v, - 40 ? c ? t a ? 85 ? c, unless otherwise noted. typical values at bp = 3.6 v and t a = 25 c under nominal conditions, unless otherwise noted. symbol characteristic min typ max unit notes sw3 buck regulator v sw3in operating input voltage ? pwm operation, 0 < il < i max ? pfm operation, 0 < il < il max 3.0 2.8 - - 4.5 4.5 v v sw3acc output voltage accuracy ? pwm mode including ripple, lo ad regulation, and transients ? pfm mode, including ripple, load regulation, and transients nom-3% nom-3% nom nom nom+3% nom+3% mv (48) i sw3 continuous output load current, v inmin < bp < 4.65 v ? pwm mode ? pfm mode - - - 50 500 - ma i sw3peak current limiter peak current detection ?v in = 3.6 v current through inductor - 1.0 - a i sw3 transient transient load change ? 100 ma/s - - 250 ma v sw3os- start start-up overshoot, il = 100 ma/s - - 25 mv t on-sw3 turn-on time ? enable to 90% of end value il = 0 - - 500 s f sw3 switching frequency ? pllx = 0 ? pllx = 1 - - 2.0 4.0 - - mhz i sw3q quiescent current consumption ? pwmps or apsmode, il = 0 ma; device not switching ? pfm mode, il = 0 ma; device not switching - - 160 15 - - a ? sw3 efficiency, ?pfm, 1.2 v, 1.0 ma ? pwm pulse skipping, 1.2 v, 120 ma ? pwm pulse skipping, 1.2 v, 250 ma ? pwm, 1.2v, 500 ma - - - - 71 79 82 81 - - - - % (49) notes: 48. transient loading for load steps of ilmax/2 49. efficiency numbers at vin = 3.6 v, excludes the qui escent current,
analog integrated circuit device data ? 55 freescale semiconductor mc34708 functional bloc k description 7.5.4.6 sw4 sw4a/b is fully integrated synchronous buck pwm voltage-mode c ontrol dc/dc regulator. it can be operated in (single phase/ dual phase mode) or as separate independent outputs. the operat ing mode of the switching regulator is configured by the sw4cfg pin. the sw4cfg pi n is sampled at startup. figure 12. sw4a/b separate output mode block diagram table 43. sw4a/b configuration sw4cfg sw4a/b config uration mode ground separate independent output vcoredig single phase vcore dual phase driver controller ea z1 z2 internal compensation sw 4in sw 4alx sw 4 afb i sen se c osw4a c in sw 4 a l sw 4 a spi interface gndsw4a sw4a sw4amode sw 4 afault v ref dac spi bp driver controller ea z1 z2 internal compensation sw4bin sw 4blx sw 4 bfb i sen se c osw 4b c in sw 4 b l sw 4 b gndsw4b sw4b sw4bmode sw 4 bfault v ref dac spi bp sw4 cfg d sw 4 a d sw 4 b
analog integrated circuit device data ? freescale semiconductor 56 mc34708 functional block description figure 13. sw4 single phase output mode block diagram driver controller ea z1 z2 internal compensation sw4in sw4alx sw4afb i sense c osw4a c insw4a l sw4a spi interface gndsw4a sw4 sw4amode sw4afault v ref dac spi bp driver controller ea z1 z2 internal compensation sw4bin sw4blx sw4bfb i sense c insw4b gndsw4b sw4bmode sw4bfault v ref dac spi bp sw4cfg vcoredig d sw4
analog integrated circuit device data ? 57 freescale semiconductor mc34708 functional bloc k description figure 14. sw4 dual phase output mode block diagram the peak current is sensed internally fo r over-current protection purposes. if an ove r-current condition is detected the regula tor will limit the current through cycle by cycle operation and alert the system through the sw4xfault spi bit and issue an scpi interrupt via the int pin. sw4a/b has a high output range (2.5 v, 3.15 v) and a low output range (1.2 v ? 1.85 v). the sw4a/b output range is set by the pums configuration at start-up and cannot be changed dynamically by software. this means that if the pums are set to allow sw4a to come up in the high output voltage ra nge, the output can only be changed between 2.5 v or 3.15 v. it cannot be programmed in the low output range. if software sets the sw4ahi[1 :0] = 00 when the pums is set to come up in the high voltage range, the output voltage will only go as low as the lowest setting in the high range, which is 2.5 v. if the pums are set to start- up in the low output voltage range, the volt age is controlled through the sw4x[4:0] bits by software, it cannot be programmed into the high voltage range. when changing th e voltage in either the high or low volt age range, the regulator should be forced into pwm mode to change the voltage. table 44. sw4a/b output voltage select sw4xhi[1:0] set point selected by output voltage 00 sw4x[4:0] see table 45 01 sw4xhi[1:0] 2.5 v 10 sw4xhi[1:0] 3.15 v 11 invalid invalid driver controller ea z1 z2 internal compensation sw4in sw4alx sw4afb i sense c osw4a c insw4a l sw4a spi interface gndsw4a sw4 sw4amode sw4afault v ref dac spi bp driver controller ea z1 z2 internal compensation sw4bin sw4blx sw4bfb i sense c osw4b c insw4b l sw4b gndsw4b sw4bmode sw4bfault v ref dac spi bp sw4cfg vcore d sw4a d sw4b
analog integrated circuit device data ? freescale semiconductor 58 mc34708 functional block description table 45. sw4a/b output voltage programmability set point sw4x[4:0] sw4x output (v) set point sw4x[4:0] sw4x output (v) 0 00000 1.2000 16 10000 1.6000 1 00001 1.2250 17 10001 1.6250 2 00010 1.2500 18 10010 1.6500 3 00011 1.2750 19 10011 1.6750 4 00100 1.3000 20 10100 1.7000 5 00101 1.3250 21 10101 1.7250 6 00110 1.3500 22 10110 1.7500 7 00111 1.3750 23 10111 1.7750 8 01000 1.4000 24 11000 1.8000 9 01001 1.4250 25 11001 1.8250 10 01010 1.4500 26 11010 1.8500 11 01011 1.4750 - - - 12 01100 1.5000 - - - 13 01101 1.5250 - - - 14 01110 1.5500 - - - 15 01111 1.5750 - - - table 46. sw4a/b electrical specifications characteristics noted under conditions bp = 3.6 v, v bus = 5.0 v, - 40 ? c ? t a ? 85 ? c, unless otherwise noted. typical values at bp = 3.6 v and t a = 25 c under nominal conditions, unless otherwise noted. symbol characteristic min typ max unit notes sw4a/b buck regulator v sw4in operating input voltage ? pwm operation, 0 < il < i max ? pfm operation, 0 < il < il max 3.0 2.8 - - 4.5 4.5 v (51) v sw4acc output voltage accuracy ? pwm mode including ripple, lo ad regulation, and transients ? pfm mode, including ripple, load regulation, and transients nom-3% nom-3% nom nom nom+3% nom+3% mv (50) i sw4 continuous output load current, v inmin < bp < 4.5 v ? pwm mode (separate) ? pwm mode single/dual phase ? pfm mode - - - - - 50 500 1000 - ma i sw4peak current limiter peak current detection ?v in = 3.6 v current through inductor (separate) ? current through inductor - - 1.0 2.0 - - a i sw4 transient transient load change, 100 ma/s ? single/dual phase ? separate - - - - 500 250 ma v sw4os- start start-up overshoot, il = 100 ma/s - - 25 mv
analog integrated circuit device data ? 59 freescale semiconductor mc34708 functional bloc k description t on-sw4 turn-on time ? enable to 90% of end value il = 0 - - 500 s f sw4 switching frequency ? pllx = 0 ? pllx = 1 - - 2.0 4.0 - - mhz i sw4q quiescent current consumption ? pwmps or aps mode, il = 0 ma; high output voltage range (v sw4x = 3.15 v or 2.5 v) device not switching ? pwmps or aps mode, il = 0 ma; low output voltage range (v sw4x = 1.3 v). device not switching ? pfm mode, il = 0 ma; device not switching - - - 500 260 15 - - - a ? sw4 efficiency ?pfm, 3.15 v, 10 ma (a) ? pwm pulse skipping, 3.15 v, 50 ma (a) ? pwm pulse skipping, 3.15 v, 250 ma (a) ? pwm, 3.15 v, 500 ma (a) ?pfm, 1.2 v, 10 ma (b) ? pwm pulse skipping, 1.2 v, 50 ma (b) ? pwm pulse skipping, 1.2 v, 250 ma (b) ?pwm 1.2 v, 500 ma (b) - - - - - - - - 79 93 92 82 72 71 81 78 - - - - - - - - % (52) notes: 50. transient loading for load steps of il max / 2. 51. when sw4a/b is set to 3.0 v and above the regulator may drop out of regulation when bp nears the output voltage. 52. efficiency numbers at v in = 3.6 v, excludes the quiescent current. table 46. sw4a/b electrical specifications characteristics noted under conditions bp = 3.6 v, v bus = 5.0 v, - 40 ? c ? t a ? 85 ? c, unless otherwise noted. typical values at bp = 3.6 v and t a = 25 c under nominal conditions, unless otherwise noted. symbol characteristic min typ max unit notes
analog integrated circuit device data ? freescale semiconductor 60 mc34708 functional block description 7.5.4.7 sw5 sw5 is fully integrated synchronous buck pwm voltage mode control dc/dc regulator. figure 15. sw5 block diagram the peak current is sensed internally fo r over-current protection purposes. if an ove r-current condition is detected the regula tor will limit the current through cycle by cycle operation and alert the syst em through the sw5fault spi bit and issue an scpi interrupt via the int pin. sw5 can be programmed in step sizes of 25 mv as shown in table 47 . if the software wants to change the output voltage, after power up the regulator should be forced into pwm mode to change the voltage. table 47. sw5 output voltage programmability set point sw5[4:0] sw5 output (v) set point sw5[4:0] sw5 output (v) 0 00000 1.2000 16 10000 1.6000 1 00001 1.2250 17 10001 1.6250 2 00010 1.2500 18 10010 1.6500 3 00011 1.2750 19 10011 1.6750 4 00100 1.3000 20 10100 1.7000 5 00101 1.3250 21 10101 1.7250 6 00110 1.3500 22 10110 1.7500 7 00111 1.3750 23 10111 1.7750 8 01000 1.4000 24 11000 1.8000 9 01001 1.4250 25 11001 1.8250 10 01010 1.4500 26 11010 1.8500 11 01011 1.4750 - - - 12 01100 1.5000 - - - 13 01101 1.5250 - - - 14 01110 1.5500 - - - 15 01111 1.5750 - - - driver controller ea z1 z2 internal compensation sw5in sw5lx sw5fb i sense c osw5 c insw5 l sw5 spi interface gndsw5 sw5 sw5mode sw5fault v ref dac spi bp d sw5
analog integrated circuit device data ? 61 freescale semiconductor mc34708 functional bloc k description table 48. sw5 electrical specifications characteristics noted under conditions bp = 3.6 v, v bus = 5.0 v, - 40 ? c ? t a ? 85 ? c, unless otherwise noted. typical values at bp = 3.6 v and t a = 25 c under nominal conditions, unless otherwise noted. symbol characteristic min typ max unit notes sw5 buck regulator v sw5in operating input voltage ? pwm operation, 0 < il < i max ? pfm operation, 0 < il < il max 3.0 2.8 - - 4.5 4.5 v v sw5acc output voltage accuracy ? pwm mode including ripple, lo ad regulation, and transients ? pfm mode, including ripple, load regulation, and transients nom-3% nom-3% nom nom nom+3% nom+3% mv (53) i sw5 continuous output load current, v inmin < bp < 4.5 v ? pwm mode ? pfm mode - - - 50 1000 - ma i sw5peak current limiter peak current detection ?v in = 3.6 v current through inductor - 1.0 - a i sw5 transient transient load change ? 100 ma/s - - 500 ma v sw5 os-start start-up overshoot, il = 0 - - 25 mv t on-sw5 turn-on time ? enable to 90% of end value il = 0 - - 500 s f sw5 switching frequency ? pllx = 0 ? pllx = 1 - - 2.0 4.0 - - mhz i sw5q quiescent current consumption ? pwmps or aps mode, il = 0 ma; device not switching ? pfm mode, il = 0 ma; device not switching - - 160 15 - - a ? sw5 efficiency ?pfm, 1.8 v, 1.0 ma ? pwm pulse skipping, 1.8 v, 50 ma ? pwm pulse skipping, 1.8 v, 500 ma ?pwm, 1.8 v, 1000 ma - - - - 80 79 86 82 - - - - % (54) notes 53. transient loading for load steps of ilmax/2 54. efficiency numbers at vin = 3.6 v, excludes the qui escent current.
analog integrated circuit device data ? freescale semiconductor 62 mc34708 functional block description 7.5.4.8 dynamic voltage scaling to reduce overall power consumption, proc essor core voltages can be varied dependi ng on the mode or activity level of the processor. sw1a/b and sw2 allow for two different set points wi th controlled transitions to av oid sudden output voltage changes , which could cause logic disruptions on their loads. preset operating points for sw1a/b and sw2 can be set up for: ? normal operation: output value selected by spi bits swx[5:0]. voltage transitions in itiated by spi writes to swx[5:0] are governed by the dvs stepping rate shown in the following tables. ? standby (deep sleep): can be higher or lower than normal operatio n, but is typically selected to be the lowest state retention voltage of a given process. set by spi bi ts swxstby[5:0] and controlled by a standby event. voltage transitions initiated by standby are governed by the swxdvsspeed[1:0] spi bits shown in table 49 . the following table summarizes the set point contro l and dvs time stepping applied to sw1a/b and sw2. the regulator have a strong sourcing and si nking capability in the pwm mode. therefor e, the rising/falling slope is determined by the regulator in pwm mode , however, if the regulators are programmed in pfm, pwmps, or aps mode during a dvs transition, the falling slope can be influenced by the load. addi tionally, as the current capabili ty in pfm mode is reduced, controlled dvs transitions in pfm mode coul d be affected. critically timed dvs trans itions are best assured with pwm mode operation. voltage transitions programmed through spi(swx[4:0]) on sw3 and sw5 will step in increments of 25 mv per 4.0 ? s, sw4a/b will step in increments of 25 mv per 8.0 ? s when sw4xhi[1:0]=00, and sw4a/b will step in increments of 25 mv per 16 ? s when sw4xhi[1:0]=00. additionally, sw3, sw4/b, and sw 5 include standby mode set point programmability. the following diagram shows the general behavior for the switch ing regulators when initiated with spi programming or standby control. sw1 and sw2 also contain power good (outputs from the mc34 708 to the application processor). the power good signal is an active high signal. when swxpwrgdb is high, it means that th e regulators output has reach ed its programmed voltage. the swxpwrgdb voltage outputs will be low during the dvs period and if the current limit is reach ed on the switching regulator. the swxpwrgd will be low from a low to high or a high to low transition of the regulator output voltage. during the dvs period, the over-current condition on the s witching regulator should be masked. if the cu rrent limit is reached outside of a dvs period , the swxpwrgd pin will stay low until the current limit condition is removed. table 49. dvs control logic table for sw1a/b and sw2 standby set point selected by 0 swx[4:0] 1 swxstby[4:0] table 50. dvs speed selection swxdvsspeed[1:0] function 00 12.5 mv step each 2.0 ? s 01 (default) 12.5 mv step each 4.0 ? s 10 12.5 mv step each 8.0 ? s 11 12.5 mv step each 16.0 ? s
analog integrated circuit device data ? 63 freescale semiconductor mc34708 functional bloc k description figure 16. voltage stepping with dvs 7.5.5 boost switching regulator swbst is a boost switching regulator with a programmable output, which defaults to 5.0 v on power up, operating at 2.0 mhz. swbst supplies the vusb regulator for the usb phy in otg mode, as well as the vbu s voltage. note t hat the parasitic leakage path for a boost regulator will cause the output voltag e swbstout and swbstfb to sit at a schottky drop below the battery voltage whenever swbst is disabled. the switching nmos transistor is integrated on-chip. an external fly back schottky diode, inductor, and capacitor are required. figure 17. boost regulator architecture swbst output voltage programmable via the swbst[1:0] spi bits as shown in table 51 . table 51. swbst voltage programming parameter voltage swbst output voltage swbst[1:0] 00 5.000 (default) 01 5.050 10 5.100 11 5.150 ? actual output voltage example actual output voltage possible output voltage window internally controlled st eps output voltage wit h light load init ial set point voltage change request internally cont rolled steps output voltage request ed set point i nit iated by spi programming , standby control request for higher voltage request for lower voltage swxpwgd 22uf 2.2uh output drive swbstlx gndswbst swbstin boosted output voltage swbst swbst swbstin bp swbstfb spi spi registers 32khz switcher core control = package pin 4.7u bp
analog integrated circuit device data ? freescale semiconductor 64 mc34708 functional block description swbst can be controlled by spi programming in pfm, pwm, an d auto mode. auto mode transitions between pfm and pwm mode based on the load curr ent. by default swbst is powered up in auto mode. table 52. swbst mode control parameter voltage swbst mode swbstmode[1:0] swbststbymode[1:0] 00 off 01 pfm 10 auto (default) 11 pwm table 53. swbst electrical specifications characteristics noted under conditions bp = 3.6 v, v bus = 5.0 v, - 40 ? c ? t a ? 85 ? c, unless otherwise noted. typical values at bp = 3.6 v and t a = 25 c under nominal conditions, unless otherwise noted. symbol characteristic min typ max unit notes switch mode supply swbst v swbst average output voltage ?3.0 v < v in < 4.5 v, 0 < il < il max nom-4% v nom nom+3% v (55) v swbstacc output ripple ?3.0 v < v in < 4.5 v 0 < il < il max , excluding reverse recovery of schottky diode - - 120 mv vp-p swbst acc average load regulation ?v in = 3.6 v, 0 < il < il max - 0.5 - mv/ma v swbst lineareg average line regulation ?3.0 v < v in < 4.5 v il = il max - 50 - mv i swbst continuous load current ?3.0 v < v in < 4.5 v, v out = 5.0 v - 380 - ma i swbstpeak peak current limit ? at swbstin, v in = 3.6 v - 1800 - ma v swbstos- start start-up overshoot, il = 0 ma - - 500 mv t on-swbst turn-on time ? enable to 90% of v out il = 0 - - 2.0 ms f swbst switching frequency - 2.0 - mhz v swbst transient transient load response, il from 1.0 to 100 ma in 1.0 s ? maximum transient amplitude - - 300 mv v swbst transient transient load response, il from 100 to 1.0 ma in 1.0 s ? maximum transient amplitude - - 300 mv v swbst transient transient load response, il from 1.0 to 100 ma in 1.0 s ? time to settle 80% of transient - - 500 s v swbst transient transient load response, il from 100 to 1.0 ma in 1.0 s ? time to settle 80% of transient - - 20 ms ? swbst efficiency, il = il max 65 80 - % i swbstbias bias current consumption ? pfm or auto mode - 35 - a
analog integrated circuit device data ? 65 freescale semiconductor mc34708 functional bloc k description 7.5.6 linear regulators (ldos) this section describes the linear regulators provided. for convenience, these regulato rs are named to indicate their typical or possible applications, but the supplies are not limited to these uses and may be applied to any loads within the specified regu lator capabilities. a low power standby mode controlled by standby is provided for the regulators with an external pass device in which the bias current is aggressively reduced. this mode is useful for deep sleep operation, where certain supplies cannot be disabled, but active regulation can be tolerated with lesser parametric requ irements. the output drive c apability and performance are limited in this mode. all regulators use the main bandgap as reference. the main bandgap is bypassed with a capacitor at refcore. the bandgap and the rest of the core circuitry are supplied from vcore. t he performance of the regulators is directly dependent on the performance of vcoredig and the bandgap. no external dc l oading is allowed on vcoredig or refcore. vcoredig is kept powered as long as there is a valid supply and/or coin cell. 7.5.6.1 general features the following applies to all linear regulators, unless otherwise specified. ? specifications are for an am bient temperature of ?40 to 85 c. ? advised bypass capacitor is the murata gr m155r60g225me95, which comes in a 0402 case. ? in general, parametric performance s pecifications assume the use of low es r x5r/x7r ceramic capacitors with 20% accuracy and 15% temperature spread, for a worst case stack up of 35% from the nominal value. use of other types with wider temperature variation may require a larger room-temperature nominal capacitance value to meet performance specs over temperature. in addition, capacitor derating as a function of dc bias voltage requires special attention. finally, minimum bypass capacitor guidelines ar e provided for stability and transient performance. larger values may be applied; performance metrics may be altered and general ly improved, but should be conf irmed in system applications. ? regulators which require a minimum output capacitor esr (thos e with external pnps) can avoid an external resistor if esr is assured with capacitor specificatio ns or board level trace resistance. ? the output voltage tolerance specified for each of the linear regulators include proc ess variation, temperature range, static line regulation, and static load regulation. ? the psrr of the regulators is measured with the perturbating si gnal at the input of the regulator. the power management ic is supplied separately from the input of the regulator and does not contain the perturbated signa l. during measurements, care must be taken not to reach the drop out of the regulator under test. ? in the low power mode, the output perfo rmance is degraded. only those parameter s listed in the low power mode section are guaranteed. in this mode, the output current is lim ited to much lower currents than in the active mode. ? regulator performance is degraded in the extended input volt age range. this means that the supply still behaves as a regulator, and will try to hold up the output voltage by turning the pass device fully on. as a result, the bias current will i ncrease and all performance parameters will be heavily degraded, such as psrr and load regulation. ? note that the minimum operating range specif ications in some cases may be conflict ing, due to numerous set point and biasing options, as well as the potential to run bp into one of the software or hardware s hutdown thresholds. the specifications are general guidelines that should be interpreted with some care in such cases. ? when a regulator gets disabled, the output will be pulled towa rds ground by an internal pull-down. the pull-down is also activated when resetb goes low. ?32 khz spur levels are specified for fully loaded conditions. i leak-swbst nmos off leakage ?swbstin = 4.5 v, swbstmode [1:0] = 0 - 1.0 6.0 a notes: 55. v in is the low side of the inductor that is connected to bp. table 53. swbst el ectrical specifications characteristics noted under conditions bp = 3.6 v, v bus = 5.0 v, - 40 ? c ? t a ? 85 ? c, unless otherwise noted. typical values at bp = 3.6 v and t a = 25 c under nominal conditions, unless otherwise noted. symbol characteristic min typ max unit notes
analog integrated circuit device data ? freescale semiconductor 66 mc34708 functional block description ? short-circuit protection (scp) is included on certain ldos (see the scp section later in this section). exceeding the scp threshold will disable the regulator and gen erate a system interrupt. the output volt age will not sag below the specified volta ge with the rated current being drawn. for the lower current ldos wit hout scp, they are less accessible to the user environment and essentially self-limiting. ? the power tree of a given application must be scrubbed for crit ical use cases to ensure consistency and robustness in the power strategy. 7.5.6.2 ldo regulator control the regulators with embedded pass devices (vpll, vgen1, and vusb) have an adaptive biasing scheme thus, there are no distinct operating modes such as a normal mode and a low power mode. therefore, no specific co ntrol is required to put these regulators in a low power mode. the external pass regulator (vdac) can also operate in a norma l and low power mode. however, since a load current detection cannot be performed for this regulator, the transition between both modes is not au tomatic and is controlled by setting the corresponding mode bits for the operational behavior desired. the regulators vusb2, and vgen2 can be configured for using the in ternal pass device or external pass device as explained in supplies. for both configurations, the tran sition between both modes is controlled by setting the vxmode bit for the specific regulator. therefore, depending on the configuration selected, the automatic low power mode determines availability. the regulators can be disabled and the general purpose outputs can be forced low when going into standby (note that the standby response timing can be altered with the stbydly function , as described in the previous section). each regulator has an associated spi bit for this. when the bit is not set, standby is of no influence. the actual operating mode of the regulator s as a function of standby is not reflected through spi. in other words, the spi will read back what is programmed, not the actua l state. for regulators with internal pass devices, the previous tabl e can be simplified by elimination of the vxmode column. table 54. ldo regulator control (external pass device ldos) vxen vxmode vxstby standby (56) regulator vx 0 x x x off 1 0 0 x on 1 1 0 x low power 1 x 1 0 on 1 0 1 1 off 1 1 1 1 low power notes 56. standby refers to a standby event as described earlier table 55. ldo regulator control (internal pass device ldos) vxen vxstby standby (57) regulator vx 0 x x off 1 0 x on 1 1 0 on 1 1 1 off notes 57. standby refers to a standby event as described earlier
analog integrated circuit device data ? 67 freescale semiconductor mc34708 functional bloc k description 7.5.6.3 transient response waveforms the transient load and line response are sp ecified with the waveforms as depicted in figure 18 . note that where the transient load response refers to the overshoot only, so excluding the dc shift itself, the transient line response refers to the sum of both overshoot and dc shift. this is also valid for the mode transition response. figure 18. transient waveforms 7.5.6.4 short-circuit protection (feature no longer suppor ted. see erratum 31.) the higher current ldos, and those most accessible in pro duct applications, include a short- circuit detection and protection (vdac, vusb, vusb2, vgen1, and vgen2) . the short-circuit protection (scp) system includes debounced fault condition detection, regulator shutdown, and processo r interrupt generation, to contain fail ures and minimize the chance of product damage. if an over-current (short-circuit) condition is detected, the ld o will be disabled by resetting its vxen bit, while at the same time, an interrupt scpi will be generate d to flag the fault to the system processor. the scpi interrupt is maskable throug h the scpm mask bit. the scp feature is enabled by setting the regscpen bit. if this bit is not set, then not only is no interrupt generated, but al so the regulators will not autom atically be disabled upon a short-circuit detection. note that by default, the regscpen bit is not set, so at startup, none of the regulat ors in an overload condition are disabled. ? 1us ? 1us 0 ? ma ? i max ? i load i load stimulus for transient load response 10us ? 10us ? v nom ? + ? 0.8v ? v in v in stimulus for transient line response ? overshoot ? i l ? = ? 0 ? ma ? v out v out for transient load response i l ? = ? i max ? overshoot ? v nom ? + ? 0.3v overshoot ? active ? mode v out v out for mode transition response (v gen2 , v usb2 , v dac ) low ? power ? mode overshoot ? i l ? < ? il max i l ? < ? il maxlp i l ? < ? il max active ? mode mode ? transition ? time
analog integrated circuit device data ? freescale semiconductor 68 mc34708 functional block description 7.5.6.5 vpll vpll is provided for isolated biasing of t he application processors plls for clock g eneration, in support of protocol and perip heral needs. depending on the application and power requirements, this supply may be considered for sharing with other loads, but noise injection must be avoided and filter ing added, if necessary to ensure suitable pll performance. the vpll regulator has a dedicated input supply pin. vinpll can be connected to either bp or a 1.8 v switched mode power supply rail such as from sw5 for the two lower set points of each regulator vpll[1:0] = [00], [01]. in addition, when the two upper set points (vpll[1:0] = [10],[11]) are used, the vinp ll inputs can be connected to either bp or a 2.2 v nominal external switched mode power supply rail, to improve power dissipation. table 56. vpll voltage control parameter value function iload max input supply vpll[1:0] 00 output = 1.2 v 50 ma bp or 1.8 v 01 output = 1.25 v 50 ma bp or 1.8 v 10 output = 1.50 v 50 ma bp or external switch 11 output = 1.8 v 50 ma bp or external switch table 57. vpll electrical specification characteristics noted under conditions bp = 3.6 v, v bus = 5.0 v,- 40 ? c ? t a ? 85 ? c, unless otherwise noted. typical values at bp = 3.6 v and t a = 25 c under nominal conditions, unless otherwise noted. symbol characteristic min typ max unit notes general v inpll operating input voltage range ? vpll all settings, bp biased ? vpll [1:0] = 00, 01 (sw5 = 1.8 v) ? vpll, [1:0] = 10, 11, external switch uvdet 1.75 2.15 - 1.8 2.2 4.5 4.5 4.5 v i pll operating current load range - - 50 ma vpll active mode ? dc v pll output voltage v out ?v inmin < v in < v inmax , ?il min < il < il max v nom ? 0.05 v nom v nom + 0.05 v v pll-lopp load regulation ?1.0 ma < il < il max for any v inmin < v in < v inmax - 0.35 - mv/ma v pll-lipp line regulation ?v inmin < v in < v inmax for any il min < il < il max - 5.0 - mv i pll-q quiescent current ?v inmin < v in < v inmax il = 0 - 8.0 - a vpll active mode ? ac vpll psrr psrr, il = 75% of il max , 20 hz to 20 khz ?v in = uvdet ?v in = v nom + 1.0 v, > uvdet 35 50 40 60 - - db vpll noise output noise density, v in = v inmin il = 75% of il max ? 100 hz ? 1.0 khz ?> 1.0 khz ? 1.0 mhz - - 20 - - 2.5 db/dec ? v/ ? hz
analog integrated circuit device data ? 69 freescale semiconductor mc34708 functional bloc k description 7.5.6.6 vrefddr vrefddr is an internal pmos half supply voltage follower. th e output voltage is at one half the input voltage. it?s typical application is as the v ref for ddr memories. a filtered resistor divider is utiliz ed to create a low frequency pole. this divider then utilizes a voltage follower to drive the load. t on-vpll turn-on time ? enable to 90% of end value v in = v inmin , v inmax il = 0 - - 120 s t off-vpll turn-off time ? disable to 10% of initial value v in = v inmin , v inmax , il = 0 0.05 - 10 ms vpll os- start start-up overshoot ?v in = v inmin , v inmax il = 0 - 1.0 2.0 % v pll-lo transient transient load response ?v in = v inmin , v inmax - 50 70 mv v pll-li transient transient line response ?il = 75% of il max - 5.0 8.0 mv table 58. vrefddr electrical specification characteristics noted under conditions bp = 3.6 v, v bus = 5.0 v, - 40 ? c ? t a ? 85 ? c, unless otherwise noted. typical values at bp = 3.6 v and t a = 25 c under nominal conditions, unless otherwise noted. symbol characteristic min typ max unit notes general v reffddrin operating input voltage range v inmin to v inmax 1.2 - 1.8 v i refddr operating current load range il min to il max 0.0 - 10 ma vrefddr active mode ? dc v refddr output voltage v out ?v inmin < v in < v inmax il min < il < il max 0.6 v in /2 0.9 v v refddrtol output voltage tolerance ?v inmin < v in < v inmax il = 1.0 ma -6.5 - 6.5 % (58) v refddr lopp load regulation ?1.0 ma < il < il max for any v inmin < v in < v inmax - 5.0 - mv/ma i refddrq quiescent current ?v inmin < v in < v inmax il = 0 - 8.0 - a vrefddr active mode ? ac t on-vrefddr turn-on time ? enable to 90% of end value v in = v inmin , v inmax il = 0 - - 100 s t off- vrefddr turn-off time ? disable to 10% of initial value v in = v inmin , v inmax , il = 0 0.05 - 10 ms v refddros start-up overshoot ?v in = v inmin , v inmax il = 0 - 1.0 2.0 % table 57. vpll elec trical specification characteristics noted under conditions bp = 3.6 v, v bus = 5.0 v,- 40 ? c ? t a ? 85 ? c, unless otherwise noted. typical values at bp = 3.6 v and t a = 25 c under nominal conditions, unless otherwise noted. symbol characteristic min typ max unit notes
analog integrated circuit device data ? freescale semiconductor 70 mc34708 functional block description 7.5.6.7 vusb2 vusb2 has an internal pmos pass fet which will support loads up to 65 ma. to support load currents an external pnp is provided. the external pnp configuration is offered to avoid e xcess on-chip power dissipation at high loads and large different ials between bp and output settings. for lower cu rrent requirements, an int egrated pmos pass fet is included. the input pin for the integrated pmos option is shared with the base current drive pin for the pnp option. the external pnp configuration must be committed as a hardwired board level implementation. th e recommended pnp device is the on semiconductor? nss12100xv6t1g, which is capable of handling up to 250 mw of continuous dissipation, at minimum footprint and 75 c of ambient. for use cases where up to 500 mw of dissipation is required, the recommended pnp device is on semiconductor nss12100uw3tcg. for stability reasons, a small minimum esr may be required. a short-circuit condition will shut down the vu sb2 regulator and generate an interrupt for scpi. the nominal output voltage of this regulat or is spi configurable, and can be 2.5 v, 2.6 v, 2.75 v, or 3.0 v. the output current when working with the internal pass fet is 65 ma, and could be up to 350 ma when working with an external pnp. v refddrl transient transient load response ?v in = v inmin , v inmax - 5.0 - mv notes 58. ?????? guaranteed at 25 c only table 59. vusb2 voltage control parameter value output voltage iload max vusb2config = 0 internal pass fet vusb2config = 1 external pnp vusb2[1:0] 00 2.5 v 65 ma 350 ma 01 2.6 v 65 ma 350 ma 10 2.75 v 65 ma 350 ma 11 3.00 v 65 ma 350 ma table 60. vusb2 electrical specification characteristics noted under conditions bp = 3.6 v, v bus = 5.0 v, - 40 ? c ? t a ? 85 ? c, unless otherwise noted. typical values at bp = 3.6 v and t a = 25 c under nominal conditions, unless otherwise noted. symbol characteristic min typ max unit notes general v usb2in operating input voltage range v inmin to v inmax v nom + 0.25 - 4.5 v i usb2 operating current load range il min to il max ? internal pass fet ? external pnp not exceeding pnp max power 0.0 0.0 - - 65 350 ma v usb2in extended input voltage range ? performance may be out of specification uvdet - 4.5 v vusb2 active mode - dc v usb2 output voltage v out ?v inmin < v in < v inmax il min < il < il max v nom - 3% v nom v nom + 3% v table 58. vrefddr el ectrical specification characteristics noted under conditions bp = 3.6 v, v bus = 5.0 v, - 40 ? c ? t a ? 85 ? c, unless otherwise noted. typical values at bp = 3.6 v and t a = 25 c under nominal conditions, unless otherwise noted. symbol characteristic min typ max unit notes
analog integrated circuit device data ? 71 freescale semiconductor mc34708 functional bloc k description v usb2lopp load regulation ?1.0 ma < il < il max for any v inmin < v in < v inmax - 0.25 - mv/ma v usb2lipp line regulation ?v inmin < v in < v inmax for any il min < il < il max - 8.0 - mv vusb2 scth short-circuit prot ection threshold internal pass fet mode ?v inmin < v in < v inmax short-circuit v out to gnd il max +20% - - ma i usb2q active mode quiescent current, v inmin < v in < v inmax ?il = 0, internal pmos configuration ?v inmin < v in < v inmax il = 0, external pnp configuration - - 25 30 - - a vusb2 low power mode - dc v usb2 output voltage v out ?v inmin < v in < v inmax il minlp < il < il maxlp v nom - 3% v nom v nom + 3% v i usb2 current load range il minlp to il maxlp 0.0 - 3.0 ma i usb2q low power mode quiescent current ?v inmin < v in < v inmax il = 0 - 8.0 10.5 a vusb2 active mode - ac vusb2 psrr psrr, il = 75% of il max 20 hz to 20 khz ?v in = v inmin + 100 mv ?v in = v nom + 1.0 v 35 50 40 60 - - db vusb 2 noise output noise density, v in = v inmin il = 75% of il max ? 100 hz ? 1.0 khz ?> 1.0 khz ? 1.0 mhz - - 20 - - 1.0 db/dec ? v/ ? hz t on-vusb2 turn-on time ? enable to 90% of end value v in = v inmin , v inmax il = 0 - - 1.0 ms t off-vusb2 turn-off time ? disable to 10% of initial value v in = v inmin , v inmax il = 0 0.05 - 10 ms vusb2 os- start start-up overshoot ?v in = v inmin , v inmax il = 0 - 1.0 2.0 % vusb2 lo transient transient load response, v in = v inmin , v inmax x ? vusb2=01, 10, 11 ? vusb2=00 - - 1.0 50 2.0 70 % mv vusb2 li transient transient line response ?il = 75% of il max - 5.0 8.0 mv t mod-vusb2 mode transition time ? from low power to active and from active to low power v in = v inmin , v inmax il = il maxlp - - 100 s vusb mode res mode transition response ? from low power to active and from active to low power v in = v inmin , v inmax il = il maxlp - 1.0 2.0 % table 60. vusb2 elec trical specification characteristics noted under conditions bp = 3.6 v, v bus = 5.0 v, - 40 ? c ? t a ? 85 ? c, unless otherwise noted. typical values at bp = 3.6 v and t a = 25 c under nominal conditions, unless otherwise noted. symbol characteristic min typ max unit notes
analog integrated circuit device data ? freescale semiconductor 72 mc34708 functional block description 7.5.6.8 vdac the primary applications of this power supply is the tv-dac. however, these supplies could also be used for other peripherals if one of these functions is not required. low power modes and programmable standby options can be used to optimize power efficiency during deep sleep modes. an external pnp is utilized for vdac to avoid excess on-chip power dissipation at high loads and large differentials between bp and output settings. for stability reas ons, a small minimum esr may be required. external pnp devices must always be connected to the bp line in the applicat ion. the recommended pnp device is the on semiconductor nss12100xv6t1g, which is capable of handling up to 250 mw of continuous dissipation at minimum footprint and 75 c of ambient. for use cases where up to 500 mw of dissipation is required, the recommended pnp devic e is on semiconductor nss12100uw3tcg. for stability reasons, an esr of 110 m ? ? 20% ? is required. a short-circuit condition will shut down the vd ac regulator and generate an interrupt for scpi. the nominal output voltage of this regu lator is spi configurable, and can be 2.5 v, 2.6 v, 2.7 v, or 2.775 v. the maximum output current along with an external pnp, is 250 ma. table 61. vdac voltage control parameter value output voltage iload max vdac 00 2.500 v 250 ma 01 2.600 v 250 ma 10 2.700 v 250 ma 11 2.775 v 250 ma table 62. vdac electrical specification characteristics noted under conditions bp = 3.6 v, v bus = 5.0 v, - 40 ? c ? t a ? 85 ? c, unless otherwise noted. typical values at bp = 3.6 v and t a = 25 c under nominal conditions, unless otherwise noted. symbol characteristic min typ max unit notes general v dacin operating input voltage range v inmin to v inmax v nom + 0.25 - 4.5 v i dac operating current load range il min to il max ? not exceeding pnp max power 0.0 - 250 ma v dacin extended input voltage range ? performance may be out of specification uvdet - 4.5 v vdac active mode ? dc v dac output voltage v out ?v inmin < v in < v inmax il min < il < il max v nom ? 3% v nom v nom + 3% v v daclopp load regulation ?1.0 ma < il < il max for any v inmin < v in < v inmax - 0.20 - mv/ma v daclipp line regulation ?v inmin < v in < v inmax for any il min < il < il max - 5.0 - mv vdac scth short-circuit prot ection threshold ?v inmin < v in < v inmax short-circuit v out to gnd il max +20% - - ma i dacq active mode quiescent current ?v inmin < v in < v inmax il = 0 - 30 - a
analog integrated circuit device data ? 73 freescale semiconductor mc34708 functional bloc k description 7.5.6.9 vgen1, vgen2 general purpose ldos, vgen1, a nd vgen2, are provided for expans ion of the power tree to suppo rt peripheral devices, which could include emmc cards, wlan, bt, gps, or other functional modules. these regula tors include programmable set points for system flexibility. vgen1 has an internal pmos pass fet, and is powered from the sw5 buck for an efficiency advantage and reduced power dissipation in the pass devices. vg en2 is powered directly from the battery. vgen2 has an internal pmos pass fe t, which will support loads up to 50 ma. for higher current capability, drive for an external pnp is provided. the external pnp is offered to avoid excess on- chip power dissipation at high loads and large differentials between bp and the output settings. the in put pin for the integrated pmos option is sh ared with the base current drive pin for the pnp option. the external pnp device is always connected to the bp line in the application. the recommended pnp device vdac low power mode ? dc - vdacmode=1 v dac output voltage v out ?v inmin < v in < v inmax il minlp < il < il maxlp v nom ? 3% v nom v nom + 3% v i dac current load range il minlp to il maxlp 0.0 - 3.0 ma i dacq low power mode quiescent current ?v inmin < v in < v inmax il = 0 - 8.0 - a vdac active mode ? ac vdac psrr psrr - il = 75% of il max 20 hz to 20 khz ?v in = v inmin + 100 mv ?v in = v nom + 1.0 v 35 50 40 60 - - db vdac noise output noise density, v in = v inmin il = 75% of il max ? 100 hz ? 1.0 khz ?> 1.0 khz ? 10 khz ?> 10 khz ? 1.0 mhz - - - - - - -115 -126 -132 ? v/ ? hz vdac spurs spurs ? 32.768 khz and harmonics - - -120 db t on-vdac turn-on time ? enable to 90% of end value v in = v inmin , v inmax il = 0 - - 1.0 ms t off-vdac turn-off time ? disable to 10% of initial value v in = v inmin , v inmax , il = 0 0.05 - 10 ms vdac os- start start-up overshoot ?v in = v inmin , v inmax il = 0 - 1.0 2.0 % vdac lo transient transient load response ?v in = v inmin , v inmax - 1.0 2.0 % v dacli transient transient line response ?il = 75% of il max - 5.0 8.0 mv t mode-vdac mode transition time ? from low power to active v in = v inmin , v inmax il = il maxlp - - 100 s vdac mode res mode transition response ? from low power to active and from active to low power v in = v inmin , v inmax il = il maxlp - 1.0 2.0 % table 62. vdac elec trical specification characteristics noted under conditions bp = 3.6 v, v bus = 5.0 v, - 40 ? c ? t a ? 85 ? c, unless otherwise noted. typical values at bp = 3.6 v and t a = 25 c under nominal conditions, unless otherwise noted. symbol characteristic min typ max unit notes
analog integrated circuit device data ? freescale semiconductor 74 mc34708 functional block description is the on semiconductor nss12100xv6t1g which is capable of handling up to 250 mw of continuous dissipation at minimum footprint and 75 c of ambient. for use cases where up to 500 mw of dissipation is required, the recommended pnp device is the on semiconductor nss12100uw3tcg. for stability, a small minimum esr may be required. a short-circuit condition will shut do wn the vgen1 and vgen2 regulators, and generate an interrupt for scpi. the nominal output voltage of vgen1 is spi configurable, and can be 1.2 v, 1.25 v, 1.3 v, 1.35 v, 1.4 v, 1.45 v, 1.5 v, or 1.55 v. the nominal output voltage of vgen2 is spi configurable, and can be 2.5 v, 2.7 v, 2.8 v, 2.9 v, 3.0 v, 3.1 v, 3.15 v, or 3.3 v. the output current when working with the internal pass fet is 50 ma, and could be up to 250 ma when working with an external pnp. table 63. vgen1 control register bit assignments parameter value output voltage iload max vgen1[2:0] 000 1.2000 250 ma 001 1.2500 250 ma 010 1.3000 250 ma 011 1.3500 250 ma 100 1.4000 250 ma 101 1.4500 250 ma 110 1.5000 250 ma 111 1.5500 250 ma table 64. vgen2 control register bit assignments parameter value output voltage iload max vgen2config=0 internal pass fet vgen2config=1 external pnp vgen2[2:0] 000 2.50 50 ma 250 ma 001 2.70 50 ma 250 ma 010 2.80 50 ma 250 ma 011 2.90 50 ma 250 ma 100 3.00 50 ma 250 ma 101 3.10 50 ma 250 ma 110 3.15 50 ma 250 ma 111 3.30 50 ma 250 ma table 65. vgen1 electrical specification characteristics noted under conditions bp = 3.6 v, v bus = 5.0 v, - 40 ? c ? t a ? 85 ? c, unless otherwise noted. typical values at bp = 3.6 v and t a = 25 c under nominal conditions, unless otherwise noted. symbol characteristic min typ max unit notes general v gen1in operating input voltage range v inmin to v inmax ? all settings 1.75 1.8 1.85 v i gen1 ? operating current load range il min to il max 0.0 - 250 ma
analog integrated circuit device data ? 75 freescale semiconductor mc34708 functional bloc k description vgen1 active mode ? dc v gen1 output voltage v out ?v inmin < v in < v inmax il min < il < il max v nom ? 3% v nom v nom + 3% v v gen1lopp load regulation ?1.0 ma < il < il max for any v inmin < v in < v inmax - 0.25 - mv/ma v gen1lipp line regulation ?v inmin < v in < v inmax for any il min < il < il max - 5.0 - mv vgen1 scth short-circuit prot ection threshold ?v inmin < v in < v inmax short-circuit v out to gnd il max +20% - - ma i gen1q active mode quiescent current ?v inmin < v in < v inmax il = 0 - 12 - a vgen1 low power mode - dc v gen1 output voltage v out ?v inmin < v in < v inmax il minlp < il < il maxlp v nom - 3% v nom v nom + 3% v i gen1 current load range il minlp to il maxlp 0.0 - 3.0 ma i gen1q low power mode quiescent current ?v inmin < v in < v inmax il = 0 - 12 - a vgen1 active mode - ac vgen1 psrr psrr ?il = 75% of il max 20 hz to 20 khz vgen1[2:0] = 000-101 ? il = 75% of ilmax 20 hz to 20 khz vgen1[2:0] = 110-111 50 37 60 - - - db vgen 1 noise output noise density, v in = v inmin il = 75% of il max ? 100 hz ? 1.0 khz ?> 1.0 khz ? 10 khz ?> 10 khz ? 1.0 mhz - - - - - - -115 -126 -132 ? v/ ? hz vgen 1 spurs spurs ? 32.768 khz and harmonics - - -100 db t on-vgen1 turn-on time ? enable to 90% of end value v in = v inmin , v inmax , il = 0 - - 1.0 ms t off-vgen1 turn-off time ? disable to 10% of initial value v in = v inmin , v inmax , il = 0 0.01 - 10 ms vgen1 os- start start-up overshoot ?v in = v inmin , v inmax , il = 0 - 1.0 2.0 % vgen1 lo transient transient load response ?v in = v inmin , v inmax - 1.0 2.0 % v gen1li transient transient line response ?il = 75% of il max - 5.0 8.0 mv table 65. vgen1 electrical specification characteristics noted under conditions bp = 3.6 v, v bus = 5.0 v, - 40 ? c ? t a ? 85 ? c, unless otherwise noted. typical values at bp = 3.6 v and t a = 25 c under nominal conditions, unless otherwise noted. symbol characteristic min typ max unit notes
analog integrated circuit device data ? freescale semiconductor 76 mc34708 functional block description t mode-vgen1 mode transition time ? from low power to active and from active to low power v in = v inmin , v inmax il = il maxlp - - 100 s vgen 1 moderes mode transition response ? from low power to active and from active to low power v in = v inmin , v inmax il = il maxlp - 1.0 2.0 % table 66. vgen2 electrical specification characteristics noted under conditions bp = 3.6 v, v bus = 5.0 v, - 40 ? c ? t a ? 85 ? c, unless otherwise noted. typical values at bp = 3.6 v and t a = 25 c under nominal conditions, unless otherwise noted. symbol characteristic min typ max unit notes vgen2 v gen2in operating input voltage range v inmin to v inmax ? all settings, bp biased v nom +0.25 - 4.5 v i gen2 operating current load range il mi to il max ? internal pass fet 0.0 - 50 ma i gen2 operating current load range il min to il max ? external pnp, not exceeding pnp max power 0.0 - 250 ma v gen2in extended input voltage range ? bp biased, performance may out of specification for output levels vgen2 [2:0] = 010 to 111 uvdet - 4.5 mv/ma co vgen2 minimum bypass capacitor value ? used as a condition fo r all other parameters 1.1 2.2 - f esr vgen2 bypass capacitor esr ?10 khz ? 1.0 mhz 20 - 100 m ? vgen2 active mode - dc v gen2 output voltage v out ?v inmin < v in < v inmax il min < il < il max v nom - 3% v nom v nom + 3% v v gen2lopp load regulation ?1.0 ma < il < il max , for any v inmin < v in < v inmax - 0.20 - mv/ma v gen2lipp line regulation ?v inmin < v in < v inmax for any il min < il < il max - 8.0 - mv vgen2 scth short-circuit prot ection threshold internal pass fet mode ?v inmin < v in < v inmax short-circuit v out to gnd ilmax +20% - - ma i gen2q active mode quiescent current ?v inmin < v in < v inmax il = 0 - 30 - a table 65. vgen1 electrical specification characteristics noted under conditions bp = 3.6 v, v bus = 5.0 v, - 40 ? c ? t a ? 85 ? c, unless otherwise noted. typical values at bp = 3.6 v and t a = 25 c under nominal conditions, unless otherwise noted. symbol characteristic min typ max unit notes
analog integrated circuit device data ? 77 freescale semiconductor mc34708 functional bloc k description vgen2 low power mode - dc - vgen2mode=1 v gen2 output voltage v out ?v inmin < v in < v inmax il minlp < il < il maxlp v nom - 3% v nom v nom + 3% v i gen2 current load range il minlp to il maxlp 0.0 - 3.0 ma i gen2q low power mode quiescent current ?v inmin < v in < v inmax il = 0 - 8.0 - a vgen2 active mode - ac vgen2 psrr psrr - il = 75% of ilmax, 20 hz to 20 khz ?v in = v inmin + 100 mv ?v in = v nom + 1.0 v 35 55 40 60 - - db vgen 2 noise output noise density - v in = v inmin il = 75% of il max ? 100 hz ? 1.0 khz ?> 1.0 khz ? 10 khz ?> 10 khz ? 1.0 mhz - - - - - - -115 -126 -132 ? v/ ? hz t on-vgen22 turn-on time ? enable to 90% of end value v in = v inmin , v inmax , il = 0 - - 1.0 ms t off-vgen2 turn-off time ? disable to 10% of initial value v in = v inmin , v inmax , il = 0 0.05 - 10 ms vgen2 os- start start-up overshoot ?v in = v inmin , v inmax il = 0 - 1.0 2.0 % vgen2 lo transient transient load response ?v in = v inmin , v inmax - 1.0 2.0 % v gen2li transient transient line response ?il = 75% of il max - 5.0 8.0 mv t mode-vgen2 mode transition time ? from low power to active v in = v inmin , v inmax , il = il maxlp - - 100 s vgen 2 moderes mode transition response ? from low power to active and from active to low power v in = v inmin , v inmax , il = il maxlp - 1.0 2.0 % table 66. vgen2 electrical specification characteristics noted under conditions bp = 3.6 v, v bus = 5.0 v, - 40 ? c ? t a ? 85 ? c, unless otherwise noted. typical values at bp = 3.6 v and t a = 25 c under nominal conditions, unless otherwise noted. symbol characteristic min typ max unit notes
analog integrated circuit device data ? freescale semiconductor 78 mc34708 functional block description 7.6 battery management battery charger no longer supported on mc34708. 7.7 analog to digital converter the adc core is a 10-bit converter. the adc core and logi c run at an internally generated frequency of approximately 1.33 mhz. the adc is supplied from vcore. the adc core has an integrat ed auto calibration circuit which reduces the offset and gain errors. 7.7.1 input selector the adc has 16 input channels. table 67 gives an overview of the characte ristics of each of these channels. some of the internal signals are first scaled to adapt the signal range to the input range of t he adc. the battery current is indirectly read out by the voltage drop over the resistor in the charge path and battery path respectively. for details on scal ing, see dedicated readings . table 67. adc inputs channel signal read input level scaling scaled version 0 battery voltage (battisnsn) 0 ? 4.8 v /2 0 ? 2.4 v 1 battery current (battisnsn-battisnsp) -80 mv ? +80 mv (59) x15 -1.2 to +1.2 v 2 application supply (bpsns) 0 to 4.8 v /2 0 ? 2.4 v 3 die temperature -40 ? 150 c x1 1.2 ? 2.4 v 4 reserved reserved reserved reserved 5 usb voltage (vbus) 0 ? 6.0 v x0.4 0 ? 2.4 v 6 reserved reserved reserved reserved 7 reserved reserved reserved reserved 8 coincell voltage 0 ? 3.6 v x2/3 0 ? 2.4 v 9 adin9 (60) 0 ? 2.4 v x1 0 ? 2.4 v 10 adin10 (60) 0 ? 2.4 v x1 0 ? 2.4 v 11 adin11 (60) 0 ? 2.4 v x1 0 ? 2.4 v 12 adin12/tsx1 (61) 0 ? 2.4 v x1/x2 0 ? 2.4 v 13 adin13/tsx2 (61) 0 ? 2.4 v x1/x2 0 ? 2.4 v 14 adin14/tsy1 (61) 0 ? 2.4 v x1/x2 0 ? 2.4 v 15 adin15/tsy2 (61) 0 ? 2.4 v x1/x2 0 ? 2.4 v notes 59. equivalent to -4.0 a to +4.0 a of current with a 20 mohm sense resistor. 60. input must not exceed the bp voltage. 61. input must not exceed bo or vcore.
analog integrated circuit device data ? 79 freescale semiconductor mc34708 functional bloc k description when considerately exceeding the maximum input of the adc at the scaled or unscaled inputs, the reading result will return a full scale. it has to be noted however, that this full scale does not necessarily yield a 1022 dec reading due to the offsets a nd calibration applied. the same applies for when going below the minimum input where the corresponding 0000 dec reading may not be returned. 7.7.2 control the adc parameters are programmed by the processor via th e spi. when a reading sequence is finished, an interrupt adcdonei is generated. the interrupt can be masked with the adcdonem bit. the adc is automatically calibrated every time the pmic is powered on. the adc is enabled by setting aden bit high. the adc can start a series of conversions through spi programming by setting the adstart bit. if the aden bit is low, the adc will be dis abled and in low power mode. the adc is automatically calibrated every time pmic is powered. the conversions will begin after a small analog synchronization of up to 30 microseconds, plus a programmable delay from 0 (default) up to 600 ? s, by programming the bits addly1[3:0]. the a ddly2[3:0] controls the delay between each of the conversions from 0 to 600 ? s. addly3[3:0] controls the delay after the final c onversion, and is only valid when adcont is high. addly1, 2, and 3 are set to 0 by default. there is a maximum of 8 conversions that will take place when th e adc is started. t he register adselx[3:0] selects the channel which the adc will read and store in the adresultx register. th e adc will always start at the channel indicated in adsel0, and read up to and including the channel set by the adstop[2:0 ] bits. for example, when adstop [2:0] = 010, it will request the adc to read channels indicated in adsel0, adsel1, and adsel2. when adstop[2:0] = 111, all eight channels table 68. adc input specification parameter condition min typ max units source impedance no bypass capacitor at input - - 5.0 kohm bypass capacitor at input 10 nf - - 30 kohm table 69. addlyx[3:0] addlyx[3:0] delay in ? s 0000 0 0001 40 0010 80 0011 120 0100 160 0101 200 0110 240 0111 280 1000 320 1001 360 1010 400 1011 440 1100 480 1101 520 1110 560 1111 600
analog integrated circuit device data ? freescale semiconductor 80 mc34708 functional block description programmed by the value in adsel0-7 will be read. when the adco nt bit is set high, it allows the adc to continuously loop and read the channels from address 0 to the stop address pr ogrammed in adstop. by default, the adcont is set low (disabled). in the continuous mode, the adhold bit will allow th e software to hold the adc seque ncer from updating the results register while the adc results are read. once the sequence of a/d conversions is complete, the adresultx results are stored in 4 spi registers (adc 4 - adc 7). 7.7.3 dedicated readings 7.7.3.1 channel 0 battery voltage the battery voltage is read at the battisnsn pin on channel 0. the battery voltage is first scaled as v(batt)/2 to fit the inpu t range of the adc. 7.7.3.2 channel 1 battery current (optional) battery current is only valid after a battery voltage reading. th e current flowing into and out of the battery can be read via the adc by monitoring the voltage drop over the sense resistor between battisnsn and battisnsp. the voltage difference between battisnsn and battisnsp is amplified to fit the adc input range as v(battisnsp - battisnsn)*15. since battery current can flow in both directio ns, the conversion is read out in 2?s complement. positive readings correspond to the current flowing into the battery, an d negative readings to the current flowing out of the battery. the value of the sense resistor used determi nes the accuracy of the result, as well as the available conversion range. note tha t excessively high values can impact the operating life of the de vice due to extra voltage drop across the sense resistor. if battery current sense is required, add a 20 m ? resistor between the battisnsn and battisnsp terminal, as shown in figure 19 . table 70. battery voltage reading coding conversion code adresultx[9:0] voltage at in put adc in v voltage at battisnsn in v 1 111 111 111 2.400 4.800 1 000 010 100 1.250 2.500 0 000 000 000 0.000 0.000 table 71. battery curr ent reading coding conversion code adresultx [9:0] voltage at input adc in mv battisnsn?battisnsp in mv current through 20 mohm in ma current flow 0 111 111 111 1200.00 80 4000 to battery 0 000 000 001 2.346 0.156 7.813 to battery 0 000 000 000 0 0 0 - 1 111 111 111 -2.346 -0.156 7.813 from battery 1 000 000 000 -1200.00 -80 4000 from battery
analog integrated circuit device data ? 81 freescale semiconductor mc34708 functional bloc k description figure 19. input configuratio n with battery current sense 7.7.3.3 channel 2 application supply the application supply voltage is read at the bp pin on channel 2. the battery voltage is first scaled as v(bp)/2 to fit the in put range of the adc. 7.7.3.4 channel 3 die temperature the relation between the read out code and temperature is given in table 73 . the actual die temperature is obtained as follows: die temp = 25 + 0.426 * (adc code - 680) 7.7.3.5 channel 4 reserved channel 4 is reserved. 7.7.3.6 channel 5 vbus voltage the vbus voltage is measured at the vbus pi n on channel 5. the vbus voltage is first sc aled in order to fit the input range of the adc by multiplying by 0.4. 7.7.3.7 channel 6 and 7 reserved channel 6 is reserved. table 72. application supply voltage reading coding conversion code adresultx[9:0] voltage at input adc in v voltage at bp in v 1 111 111 111 2.400 4.800 1 000 010 101 1.250 2.500 0 000 000 000 0.000 0.000 table 73. die temperature voltage reading parameter min typ max unit die temperature read out code at 25 c - 680 - decimal slope temperature change per lsb - +0.426 - c/lsb slope error - - 5.0 % chrgfb battisnsn battisnsp bp gbat bpsns batt bp r1 20m 10u 10u c1 c2 input/battery monitoring battery
analog integrated circuit device data ? freescale semiconductor 82 mc34708 functional block description 7.7.3.8 channel 8 coin cell voltage the voltage of the coin cell connected to the licell pin can be read on channel 8. since the voltage range of the coin cell exceeds the input voltage range of the adc, the licell voltage is scaled as v(licell)*2/3. see . 7.7.3.9 channel 9-11 adin9-adin11 there are 3 general purpose analog input channels th at can be measured through the adin9-adin11 pins. 7.7.3.10 channel 12-15 adin12-adin15 if the touch screen is not used, the inputs tsx1, tsx2, tsy1, and tsy2 can be used as general purpose inputs. they are respectively mapped on adc channels 12, 13, 14, and 15. 7.7.4 touch screen interface the touch screen interface provides all ci rcuitry required for the read out of a 4-wire resistive touch screen. the touch screen x plate is connected to tsx1 and tsx2, while the y plate is co nnected to tsy1 and tsy2. a local supply tsref will serve as a reference. several readout possibilities are offered. if the touchscreen is not used, the inputs tsx1, tsx2, tsy1 , and tsy2 can be used as gener al purpose inputs. they are respectively mapped on adc channels 12, 13, 14, and 15. touch screen pen detection bias can be en abled via the tspendeten bit in the ad0 register. when this bit is enabled and a pen touch is detected, the tspendet bit in the interrupt status 0 regist er is set and the int pin is asserted - unless the inte rrupt is masked. pen detection is onl y active when tsen is low. the reference for the touch screen (touch bias) is tsref and is powered from vcore. during touch screen operation, tsref is a dedicated regulator. no loads other than the touch screen should be connect ed here. when the adc performs non touch screen conversions, the adc does not rely on tsref and the reference is disabled. the readouts are designed such that the on chip switch resi stances are of no influence on the overall readout. the readout scheme does not account for contact resistances, as present in the touch screen connectors. the touch screen readings will have to be calibrated by the user or the fa ctory, where one has to point with a stylus to the opposite cor ners of the screen. w hen reading the x-coordinate, the 10 -bit adc reading represents a 10-bit coordinate , with ?0? for a coordinate equal to x-, and ful l scale ?1023? when equal to x+. when reading the y-coordinate, th e 10-bit adc reading represents a 10-bit coordinate, with ?0? for a coordinate equal to y-, and full scale ?1023? when equal to y+. when reading contact resistance, the 10-bit adc reading represents the voltage drop ov er the contact resistance created by th e known current source, multiplied by 2. the x-coordinate is determined by applyi ng tsref over the tsx1 and tsx2 pins, while performing a high-impedance reading on the y-plate through tsy1. the y-coordinate is determined by applying tsref between tsy1 and tsy2, while reading the tsx1 pin. the contact resistance is measured by applying a known current into the tsy1 pin of the touch screen and through the tsx2 pin, which is grounded. the vo ltage difference between the two remaining terminals tsy2 and tsx1 is measured by the adc, and equals the voltage across the contact resistance. me asuring the contact resistance helps determine if the touch screen is touched with a finger or a stylus. the tsselx[1:0] allows the application processor to select it s own reading sequence. the tsselx[1:0] determines what is read during the touch screen readi ng sequence, as shown in table 75 . the touchscreen will always start at tssel0 and read up to and including the channel set by tssel at the tsstop[2:0] bits. for example w hen tsstop[2:0] = 010, it will request the adc to read channels indicated in tssel0, tssel1, and tssel2. when tsstop[2:0] = 111, all eight addresses will be read. table 74. coin cell voltage reading coding conversion code adresultx[9:0] voltage at adc input (v) voltage ? at ? licell (v) 1 111 111 110 2.400 3.6 1 000 000 000 1.200 1.8 0 000 000 000 0.000 0
analog integrated circuit device data ? 83 freescale semiconductor mc34708 functional bloc k description the touch screen readings can be repeated, as in the following example readout sequence, to reduce the interrupt rate and to allow for easier noise rejection. the dummy conversion inserted between the different readings allows the references in the system to be pre-biased for the change in touch screen plate polarity. it will read out as ?0?. a touchscreen reading will take precedence over an adc sequence. if an adc reading is triggered during a touchscreen event, the adc sequence will be overwr itten by the touchscreen data. the first touch screen conversion can be delayed from 0 (default) to 600 ? s by programming the tsdly1[3:0] bits. the tsdly2[3:0] controls the delay between each of the touch screen conversions from 0 to 600 ? s. tsdly[2:0] sets the delay after the last address is converted. tsdl y1, 2, and 3 are set to 0 by default. to perform a touch screen reading, t he processor must do the following: ? enable the touch screen with tsen ? select the touch screen sequence by pr ogramming the tssel0-tssel7 spi bits. ? program the tsstop[2:0] ? program the delay between the conversi on via the tsdly1 and tsdly2 settings. ? trigger the adc via the tsstart spi bit ? wait for an interrupt indicating the conversion is done tsdonei ? and then read out the data in the adresultx registers table 75. touch screen action select tsselx[1:0] signals sampled 00 dummy to discharge tsref cap 01 x plate 10 y ?plate 11 contact table 76. tsdlyx[3:0] tsdlyx[3:0] delay in us 0000 0 0001 40 0010 80 0011 120 0100 160 0101 200 0110 240 0111 280 1000 320 1001 360 1010 400 1011 440 1100 480 1101 520 1110 560 1111 600
analog integrated circuit device data ? freescale semiconductor 84 mc34708 functional block description 7.7.5 adc specifications table 77. adc electrical specifications characteristics noted under conditions bp = 3.6 v, v bus = 5.0 v, - 40 ? c ? t a ? 85 ? c, unless otherwise noted. typical values at bp = 3.6 v and t a = 25 c under nominal conditions, unless otherwise noted. symbol characteristic min typ max unit notes adc i conver conversion current - 1.0 - ma v adcin converter core input range ? single ended voltage readings ? differential readings 0.0 -1.2 - - 2.4 1.2 v t convert conversion time per channel - - 10 ? s integral non-linearity - - 3.0 lsb differential non-linearity - - 1.0 lsb zero scale error (offset) - - ? 5.0 lsb full scale error (gain) - - ? 10 lsb drift over temperature - - 1.0 lsb t on-off-adc turn on/off time - - 31 ? s battery current reading (62) amplifier gain 19 20 21 amplifier offset -2.0 - 2.0 mv sense resistor - 20 - m ? die temperature voltage reading die temperature read out code at 25 c - 680 - decimal slope temperature change per lsb - 0.426 - c/lsb slope error - - 5.0 % notes 62. amplifier bias current account ed for in overall adc current drain
analog integrated circuit device data ? 85 freescale semiconductor mc34708 functional bloc k description 7.8 auxiliary circuits 7.8.1 general purpose i/os the mc34708 contains four configurable gpio input/outputs for g eneral purpose use. when configured as outputs, they can be configured as open-drain (od) or cm os (push-pull outputs). these gpios are low voltage capable (1.2 or 1.8 v). in open drain configuration these outputs ca n only be pulled up to 2.5 v maximum. each individual gpio has a dedicated 16-bit control register. table 78 provides detailed bit descriptions. table 78. gpiolvx control spi bit description dir gpiolvx direction 0: input (default) 1: output din input state of the gpiolvx pin 0: input low 1: input high dout output state of gpiolvx pin 0: output low 1: output high hys hysteresis 0: cmos in 1: hysteresis (default) dbnc[1:0] gpiolvx input debounce time 00: no debounce (default) 01: 10 ms debounce 10: 20 ms debounce 11: 30 ms debounce int[1:0] gpiolvx interrupt control 00: none (default) 01: falling edge 10: rising edge 11: both edges pke pad keep enable 0: off (default) 1: on ode open drain enable 0: cmos (default) 1: od dse drive strength enable 0: 4.0 ma (default) 1: 8.0 ma pue pull-up/down enable 0: pull-up/down off 1: pull-up/down on (default)
analog integrated circuit device data ? freescale semiconductor 86 mc34708 functional block description 7.8.2 pwm outputs there are two pwm outputs on the mc34708 pwm1 and pwm2 and which are controlled by the pwmxduty and pwmxclkdiv registers shown in table 79 .the base clock will be the 2.0 mhz divided by 32. 32.768 khz crystal oscillator rtc block de scription and application information pus[1:0] pull-up/pull-down enable 00: 10 k active pull-down 01: 10 k active pull-up 10: 100 k active pull-down 11: 100 k active pull-up (default) sre[1:0] slew rate enable 00: slow (default) 01: normal 10: fast 11: very fast x= 0, 1, 2, or 3 table 79. pwmx duty cycle programming pwmxdc[5:0]( (63) ) duty cycle 000000 0/32, off (default) 000001 1/32 ? ? 010000 16/32 ? ? 011111 31/32 1xxxxx 32/32, continuously on notes 63. ?x? represent 1 and 2 table 80. pwmx clock divider programming pwmxclkdiv[5:0]( (64) ) duty cycle 000000 base clock 000001 base clock / 2 ? ? 001111 base clock / 16 ? ? 111111 base clock / 64 notes 64. ?x? represent 1 and 2 table 78. gpiolvx control spi bit description
analog integrated circuit device data ? 87 freescale semiconductor mc34708 functional bloc k description 7.8.3 general purpose led drivers by default, the general purpose le d drivers are set to auto usb charger detect. if the vbus pin is connect ed to detect what kin d of accessory is attached to the usb port, the red led can illumi nate when a charger is attached in the following use case. if t he both the main battery is dea d (battery < uvdet) and coincell is dead (licell < 1.8 v) and power is applied to vbus > 4.35 v, the red led will automatically turn on. if the coincell (licell > 1.8 v) or battery > uvdet and the chren bit is se t to 0, and power is applied to vbus > 4.35 v, the led's will stay off. to turn on the led's the following bits must be set, chrledxen = 1, chrgledovrd =1, therm bit = 1, and programming the duty cycle > 0/32. the general purpose led drivers, chrgledr, and chrledg are independent current sink channels. each driver channel features programmable current levels via chrgledx[1 :0], as well as programmable pwm duty cycle settings with chrgledxdc[5:0]. by a combin ation of level and pwm settings, each channel provi des flexible led intensit y control. by driving leds of different colors, color mixing can be achieved. the general purpose led drivers include ramp up and ramp down patterns implemented in hardware. ramping is enabled for each of the drivers using the corresponding chrgledxramp bits, only when the repetition rate is 256 hz. table 81. led driver control therm chrgledxen (65) chrgledovrd chrgledx (65) x 0 (default) 0 auto usb charger detect 1 x x off 0 1 1 on 0 1 off notes 65. ?x? represents r or g table 82. general purpose led drivers current programming chrgledx[1:0] chrgledx current level (ma) 00 3.4 01 6.6 (default) 10 9.8 11 12.5 ?x? represents for r, and g table 83. general purpose led drivers duty cycle programming chrgledxdc[5:0] duty cycle 000000 0/32, off 000001 1/32 ? ? 010000 16/32 ? ? 011111 31/32 1xxxxx 32/32, continuously on ?x? represents r, and g
analog integrated circuit device data ? freescale semiconductor 88 mc34708 functional block description the ramp itself is generated by increasi ng or decreasing the pwm duty cycle with a 1/32 step every 1/64 seconds. the ramp time is therefore a function of the init ial set pwm cycle and the final pwm cycle. as an example, starting from 0/32 and going to 32/32 will take 500 ms, while going to from 8/32 to 16/32 takes 125 ms. note that the ramp function is executed upon every change in pwm cycle setting. if a pwm change is programmed via the spi when chrgledxramp = 0, the change is immediate rather than spread out over a pwm sweep. for color mixing and to guarantee a constant color, the color mixi ng should be obtained by the current level setting, so the intensity is set thro ugh the pwm duty cycle. in addition, programmable blink rates are provided. blinking is ob tained by lowering the pwm repetition rate of each of the dri vers through chrgledxper[1:0], while the on period is determined by the duty cycle setting. to avoid high frequency spur coupling in the application, the s witching edges of the output drivers are softened. table 84. general purpose led drivers period control chrgledxper[1:0] repetition rate units 00 256 hz 01 8.0 hz 10 1.0 hz 11 1/2 hz table 85. led driver electrical specifications characteristics noted under conditions bp = 3.6 v, - 40 ? c ? t a ? 85 ? c, unless otherwise noted. typical values at bp = 3.6 v and t a = 25 c under nominal conditions, unless otherwise noted. symbol characteristic min typ max unit notes general purpose led driver absolute accuracy - - 30 % matching - at 1.0 v, 12 na - - 4.0 % leakage - chrglaedxdc [5:0]=000000 - - 1.0 ? a
analog integrated circuit device data ? 89 freescale semiconductor mc34708 functional bloc k description 7.8.4 mini/micro usb switch the mc34708 is able to multiplex the 5 pins to support uart and high-speed usb2.0 data communications, a mono/stereo- audio/microphone headset, or other accessories. to identify what accessory is plugged into the mini or micro-usb connector, the mc34708 supports various detection mechanisms, including th e vbus detection and id detection. a highly accurate 5-bit adc is offered to distinguish the 32 levels of id resistance, a nd to identify the button pressed in a cord remote control, whil e an audio type 1 cable is attached. after identifying the accessory attached, the mc34708 configures itself to support the accessor y and interrupts a host via the int pin. the processor can evaluate what caused the interrupt via the spi/i 2 c bus. the mc34708 is also able to identify some non-supported accessori es, such as video cables, phone-powered devices, etc. figure 20. usb interface 7.8.4.1 supplies the mc34708 provides the regulators required to power the phy in the i.mx50, i.mx51, a nd i.mx53 processors, which are vusb2 (detailed linear regulators (ldos) ), and vusb. the ic also provides the 5.0 v supply for usb otg operation. the vusb regulator is used to supply 3.3 v to the external usb phy. the input to the vusb regulator can be supplied from the vbus wire of the cable when supplied by a host (pc or hub), or by the swbst voltage via the vi nusb pin. the vusb regulator is powered from the swbst boost supply to ensure otg curre nt sourcing compliance through the normal discharge range of the main battery. the vusbsel spi bit is used to make the selection between a host or otg mode operation. id vbus vusb vusb2 uart usb audio gnd id vbus vinusb vusb vinusb2 vusb2 dp dm txd rxd d+ d- spkr spkrl mic vbus m0 m1 motg switches switches switches regulator regulator detect detect to/from application processor to/from audio ic to/from mini-usb connector swbst (5.0 v boosted supply) 3.3 v usb analog supply bp 2.5v usb analog supply to/from mini-usb connector
analog integrated circuit device data ? freescale semiconductor 90 mc34708 functional block description the vusb regulator defaults to on when pums4:1 = [0100], and is supplied by the swbst output. as shown in figure 20 , this means that the m0 and motg switches are open, while the m1 switch is closed. when pums4:1 is not equal to [0100], the vusb regulator can not be enabled unless 5.0 v is present on the vbus pin. if vbus is detected during a cold st art, then the vusb regulator will be enabled and powered on in the sequence shown in startup requirements , and it will default to be supplied by the vbus pin. this m eans that switch m0 is clos ed and switch m1 and motg in figure 20 are open. if vbus is not detected at cold start, then the vusb regulator cannot be enabled. if vbus is detected later, the vusb regulator will be enabled automatically and supplie d from the vbus pin. the vusben spi bit is initialized at startup, based on the pums4:1 configuration. with pums4:1 no t equal to [0100], the vusben spi bit will default to a one on power up and will reset to a 1, when either resetb is valid or vbus is inva lid. this allows the vusbe n regulator to be enabled automatically if the vusb regulator was disabled by software. with pums4:1 equal to [0100], the vusben bit will be enabled in the power up sequence. the mc34708 also supports usb otg mode by supplying 5.0 v to the vbus pin. the otgen spi bit along with the vusbsel spi bit, control switching the swbst to drive vbus in otg mode. when otgen = 1 and vusbsel = 1, swbst will be driving the vbus (switch m1 and motg are closed, and the m0 switch is open). when otg m ode is disabled, the switch (motg) from vinusb to vbus will be open. in otg mode, the vusb regulator is enabl ed by setting the vusben spi bit to a one. when swbst is supplying the vbus pin (otg mode), it will generate a usbdet interrupt. the usbdet in terrupt while in otg mode should not be interpreted as being powered by the host by software. table 86. vusb input source control (66) parameter value function v usbsel 0 powered by host: vbus powers vusb regul ator (switch m0 closed and m1 open) 1 otg mode: swbst internally switch ed to supply the vusb regulator (s witch m1 closed, m0 open), and swbst will drive vbus from the vinusb pin as long as spi bit otgen is set = 1. notes 66. vusbsel = 1 and otgen = 1 only close the switch between the vinusb and vbus pins, but do not enable the swbst boost regulator (which should be enabled with swbsten = 1) table 87. vusb/otg switch configuration mode otgen vusbsel switches enabled (closed) switches disabled (open) vusb powered from vbus pin 0 0 m0 m1, motg vusb powered from vinusb pin 0 1 m1 m0, motg invalid option 1 0 - - otg mode (vusb powered from vinusb pin and swbst 1 1 m1, motg m0 table 88. vusb electrical characteristics characteristics noted under conditions bp = 3.6 v, v bus = 5.0 v, - 40 ? c ? t a ? 85 ? c, unless otherwise noted. typical values at bp = 3.6 v and t a = 25 c under nominal conditions, unless otherwise noted. symbol characteristic min typ max unit notes vusb regulator v usbin operating input voltage range v inmin to v inmax ? supplied by vbus ? supplied by swbst 4.4 - 5.0 - 5.25 5.75 v i usb operating current load range il min to il max 0.0 - 100 ma co vusb bypass capacitor value range 0.65 2.2 - ? f esr vusb bypass capacitor esr ?10 khz - 1.0 mhz 0.0 - 0.1 ?
analog integrated circuit device data ? 91 freescale semiconductor mc34708 functional bloc k description 7.8.4.2 accessory identification the mc34708 monitors both the id pin and the vbus pin. w hen an accessory at tachment is detect ed, the accessory identification state machine will enter active mode to start t he identification flow. the id de tection state machine will deter mine what id resistor is attached and the power supply type identi fication or psti circuit will determine what type of power supply is connected. the 32 khz crystal must be placed across the xtal 1 and xtal2 pins for the accessory identification to work. an identification conclusion is made when the identification flow is finished. the corresponding bit in the usb device type/sta tus register is set to indicate the device type, and the attach bit in the usb interrupt status regi ster is set to inform the baseb and. if the attached accessory can't be ident ified, the unknown_atta bit in the u sb interrupt status register is set. there are three types of accessories that the mc34708 will automatically detect. 1. recognized and supported. the following accessories are id entified and configured automat ically: usb port, uart, audio type 1 cable, tty accessory, usb jig cables, and uart jig cables. 2. recognized but not supported. the following accessories can be identified but are not supported by the mc34708 pmic: a/v cables, phone-powered devices, audio type 2 cables, dedi cated charger, usb charger, a/v charger, 5-wire type 1 and type 2 chargers. the pmic will detect that a charger is attached, when the vbus vo ltage transitions above the setpoint, which is defaulted to 4.35 v. when above this threshold for longer than the debounce period (vbusdb[1:0]), the usbdet interrupt is generated and usbdets is set to a one. when the vbus input falls below the vbustl[2:0] threshold, the usbdet interrupt is generated immediately without any debou nce and the usbdets bit is low. see table 89 and table 90 . the usbovp interrupt will be triggered when an over-voltage on vbus (>6.5 v typical) is detected during a device attach. the over-voltage interrupt is debounce by sup_ovp_db[1:0] bits on table 91 . vusb active mode - dc v usb output voltage v out ?v inmin < v in < v inmax il min < il < il ma v nom - 4% 3.3 v nom + 4% v v usblopp load regulation ? 0 < il < il max from dm / dp, for any v inmin < v in < v inmax - 1.0 - mv/ma v usblipp line regulation ?v inmin < v in < v inmax , for any il min < il < il max - - 20 mv v usbscth short-circuit prot ection threshold ?v inmin < v in < v inmax , short-circuit v out to ground i max +20% - - ma t off-vusb turn-off time ? disable to 0.8 v, per usb otg specification parameter va_sess_vld v in = v inmin , v inmax il = 0 - - 1.3 sec vusb active mode - ac vusb psrr psrr - il = 75% of il max 20 hz to 20 khz ?v in = v inmin + 100 mv 35 40 - db vusb noise output noise - v in = v inmin il = 75% of il max ? 100 hz ? 50 khz ?> 50 khz ? 1.0 mhz - - - - 1.0 0.2 ? v/ ? hz table 88. vusb elect rical characteristics characteristics noted under conditions bp = 3.6 v, v bus = 5.0 v, - 40 ? c ? t a ? 85 ? c, unless otherwise noted. typical values at bp = 3.6 v and t a = 25 c under nominal conditions, unless otherwise noted. symbol characteristic min typ max unit notes
analog integrated circuit device data ? freescale semiconductor 92 mc34708 functional block description ? 3. not recognized accessories. all accessories that are not recognized are identified as unknown accessories. table 89. vbus debounce times vbusdb[1:0] debounce time (ms) 00 0 01 10 10 20 11 30 table 90. vbus high/low detection threshold vbusth[2:0] voltage vbustl[2:0] voltage 000 4.05 000 3.55 001 4.15 001 3.65 010 4.25 010 3.75 011 4.35 (default) 011 3.85 (default) 100 4.45 100 3.95 101 4.55 101 4.05 110 4.65 110 4.15 111 4.75 111 4.25 table 91. over-voltage debounce time sup_ovp_db[1:0] sup_ovp_db[1:0] debounce time 00 0 (default 1.0) 01 2 rtc clock cycles 10 4 rtc clock cycles 11 8 rtc clock cycles (default 2.0)
analog integrated circuit device data ? 93 freescale semiconductor mc34708 functional bloc k description figure 21. identification flow state diagram 7.8.4.3 id identification a comparator monitors the id pin impedance to ground. when a resistor less than 1.0 m ? is connected between the id line and the ground, the id_floats bit in the interr upt sense 0 register will be se t to 0. when the resistor is removed, the id_floats bit will be set to 1. a falling edge of this bit starts the id entification flow, and a rising ed ge starts the detachment detect ion flow. the id_det_end signal is used to indicate the end of the identification. after the id_floats bit is set to 0, the i dentification flow is started, and an adc_en signal is set to enable an adc conversio n. a 5-bit id adc is used to measure the id resistance. the adc is al so used to identify what button is pressed in a cord remote control when the attached accessory is an audio type 1 cable. when the conversion completes, an adc_status bit is set and the adc result value is sent to the adc manual sw/result register. the adc_en signal is cleared au tomatically after the conversion finishes. if the id resistance is below 2.0 k ? , the adc result is set to 00000. if the id lin e is floating, the adc result is set to 11111. 7.8.4.4 stuck key identification when the adc conversion is finished and the adc result is fou nd to be a value corresponding to a remote control key of audio type 1 cable, a stuck key process flow will be initiated to det ermine whether a remote control key is stuck and to inform the baseband of the stuck key status. figure 22 shows the stuck key process flow. if the stuck key is detected to be released within 1.5 s, the flow will re turn to re-start the id identification flow. other wise, a stuck_key interrupt is set. when the key is released, a stuck_key_rcv interrupt is generated, and the identif ication flow is re-started to determine the id resistance of the attached cable. vbus_det? detection delay usb host usb-otg r id = usb jig w/ boot? usb jig cable w/ boot option unknown id_float? r id < 100 ? ? r id = 75 ? ? video cable start adc to measure r id r id = uart jig w/ boot? r id = audio type 1 ? audio type 1 r id = 102k ? ? phone powered device yes no no yes yes yes yes yes yes yes no no no no no no r id = video cable? no yes r id = usb jig w/o boot? usb jig cable w/o boot option yes no uart jig cable w/ boot option r id = uart jig w/o boot? yes no uart jig cable w/o boot option r id = tty converter? tty converter yes r id = uart cable? uart cable yes no no dp ? 0.6v dm < 0.4v? yes no dm > 0.8v no yes no id_float? yes id_float? no yes a/v_chg = 1 id_det_en d? yes no standby active (identification flow) r id = audio type2 cable? audio type2 cable yes dedicated charger r id = 440k ? ? r id = 200k ? ? 5-wire charger no yes yes no no id_float id_det_en d? yes no yes dm ? 0.6v dp < 0.4v? no yes usb charger adc = 00000 no r id = remote key? no yes stuck key process id_det_en d? no yes video cable? yes no reset
analog integrated circuit device data ? freescale semiconductor 94 mc34708 functional block description figure 22. stuck key process flow diagram 7.8.4.5 power supply type identification the psti (power supply type identification) circuit is used in active mode to identify the type of the connected power supply. the psti circuit first detects whether the dp and dm pins are shor ted. if the dp and dm pins ar e found to be shorted, the psti circuit will continue to determine whether dp and dm pins are a fo rward short or reverse short. the detection result, together with the id detection result, is used to det ermine what powered accessory is connected. the psti circuit is shown in figure 23 . its operation is described as follows. when the mc34708 detects that the vbus_det bit is set, the psti ident ification flow starts. 1. wait for a detection delay t d (programmable in the usb time delay register). 2. during t d , check to see whether id_float = 0. if yes, then wa it for the id_det_end to be set and check whether the attached accessory is an a/v cable. 3. if the result is an a/v cable, set the a/v_chg and attach interrupt bits, as well as the a/v bit in usb device type/status register, to inform the baseband and finish the identification flow. if not, go to step 4. 4. enable the psti (psti_en set to '1') at t1. when psti_en rises, the sw1 swit ch is turned on to drive the vdat_src data source voltage to dp line. in the meantime, the sw2 s witch is turned on so the idat _sink current source sinks a current from the dm line. at t2, the psti starts to compare the dm line voltage with references vdat_ref and vcr_ref. if the dm line voltage stays above vdat_ref, but below vcr_ref for 20 ms continuously before t4, which means that the dp and dm pins are shorted, the dp/dm_short signal is set to '1' at t3. go to step 5. if the dp and dm ar e not shorted, the vbus detection completes at t4 and the vbus_det_end is set to '1'. the state machine will go to step 6 to determine the type of accessory, based on the dm voltage. 5. the state machine checks if the id pin is floating. if the id pin is not fl oating at t3, the psti ci rcuit turns off sw1 and s w2, and the vbus detection completes. the vbus_det_end is set to '1' and the state machine goes to step 6. if the id pin is floating at t3, the psti circuit turns off sw1 and sw2, and then turns on sw3 and sw4 to force vdat_src to the dm pin. if the dp pin is between the two thresholds vdat_ref and vcr_ref for 20 ms continuously before t6, it means that the dp and dm pins are a reverse short.the dp/dm_reverse_s hort is set to '1' at t5, the sw3 and sw4 are turned off, vbus_det_end is set to '1', and the state machine goes to step 6. if dp and dm are not a reverse short, the vbus detection completes at t6, sw3 and sw4 are turned off, the vbus_det_end is set to '1', and the state machine goes to step 6. 6. the state machine decides on the attached accessory, based on the id identificatio n, and the vbus identification results.
analog integrated circuit device data ? 95 freescale semiconductor mc34708 functional bloc k description figure 23. power supply type identification circuit block diagram figure 24. operating waveforms for the psti circuit
analog integrated circuit device data ? freescale semiconductor 96 mc34708 functional block description the mc34708 contains registers which hold co ntrol and status information. the register map and the description of each register can be found in the spi/i2c register map section. the details of some important control bits are described as follows. table 92. timing delays for psti circuit characteristics noted under conditions bp = 3.6 v, v bus = 5.0 v, - 40 ? c ? t a ? 85 ? c, unless otherwise noted. typical values at bp = 3.6 v and t a = 25 c under nominal conditions, unless otherwise noted. symbol characteristic min typ max unit notes switching delay t d t1 - t0 (t d in default value is td = 0100) ?td = 0000 ?td = 0001 ?td = 0010 ?td = 0011 ?td = 0100 ? ... ?td = 1111 - - - - - ... - 100 200 300 400 500 ... 1600 - - - - - ... - ms t sw t2 - t1 20 - - ms t sw t3 - t2 20 - - ms t sw t4 - t1 100 - - ms t sw t6 - t3 100 - - ms
analog integrated circuit device data ? 97 freescale semiconductor mc34708 functional bloc k description 7.8.4.6 control functions 7.8.4.6.1 timing of the s witching action (wait bit) if the wait bit is '1' when the attach inte rrupt bit is set, the mc34708 waits for a wa it time before turning on the switches. the wait time is programmed by the switching wait bits in the timi ng set 2 register. if the wait bit is '0' when the attach interru pt is generated, then the mc34708 will not turn on the switches until the wait bit is set to '1' by the spi. both cases are shown in figure 25 . figure 25. operating waveforms of the wait bit 7.8.4.6.2 automatic switchi ng or manual switching (switc h_open & manual s/w bits) when a supported accessory is identified, the default behavior of the mc34708 automat ically turns on the corresponding signal switches. the user can also choose to turn on optional signal switches manually. switch turn on is controlled by the manual ? s/w bit and the switch_open bits in the usb manual sw/resul t and usb control/device mode registers respectively. if the switch_open bit is '0', the audio, uart, and usb switches are off. if manual s/w = 1, which is its reset valu e, the switches to be turned on and the out puts of the jig and boot pins are determin ed automatically by the device mode register, which is the identif ication result. if manual s/w = 0, the switches to be turned on are determined by the values of the usb manual sw/result register. the relationship between the values of the usb manual sw/ result register and the switches to be turned on is found in spi/i2c register map section. the values of the switch_open and manual s/w bits will not affect the identification flow and the timing of the signal switchin g action of the mc34708. the difference between manual s/w = 1 and manual s/w = 0 is what switches are turned on. in both cases, no switches are turned on in sta ndby mode. if the manual s/w bit is changed from '1' to '0' while an accessory is attach ed, the already automatically turned on switches will be turned off, and the s witches selected manually wil l be turned on. however, writing the manual s/w bit back to '1' in active mode wil l not change the switches and outputs status. setting the switch_open = 1, sets the switch es according to the manual s/w bit. ?
analog integrated circuit device data ? freescale semiconductor 98 mc34708 functional block description raw data (raw data bit) the raw data bit functions only when the accessory is audio ty pe 1, which supports the remo te control key. the raw data bit determines whether to report the id pin resistance change to the baseband when any key is pressed. when raw data = 1, the adc is enabled only when an id line event is detected, such as when a key is pressed. in this case, the interrupt bits kp, lkp, or lkr, and the corresponding button bits in button 1 a nd button 2 registers, will be set accordingly. detailed behavior information when raw data = 1 can be found in audio type 1 operation mode . audio device type 1 - audio with or without the remote contro l. when raw data = 0, the adc is enabled periodically to calculate the id line resistance. any change of adc result will set the adc_change interrupt bit to inform the baseband. the baseband can read the adc result via the spi. the kp, lkp, or lkr, and the button bits, will not set when raw data = 0. the period of adc conversion is determined by the device wake-up bi ts in the usb timing register. all other behaviors of audio type 1 and other accessories will not be affected by the raw data bit. lkr and the button bits will not set when raw data = 0. the period of adc conversion is determined by the device wake-up bits in the timing set 1 register. all other behaviors of audi o type 1 and other accessories will not be affected by the raw data bit. 7.8.4.7 analog and digital switches the signal switches in the mc34708 are shown in figure 26 . these switches are controlled by the identification result when the manual s/w = 1, and by the manual sw/result register, when the manual s/w = 0 is in active mode. the switch_open bit overrides the switch configuration. when th e switch_open bit is 0, all sw itches are turned off. the switches for the spk_l and spk_r are capable of passing signals of ? 1.5 v, referencing to the g nd pin voltage. the spk_l and spk_r pins are pulled down to gnd via a 100 k ? resistor respectively, as shown in figure 26 . when the switches are conf igured automatically by the identification result, the configuration of the switches vs. the device type is shown in table 93 . when detachment of an accessory is detect ed, the mc34708 will return to standby mo de. in standby mode, regardless of the manual s/w = 1 or manual s/w = 0 state, a ll signal switches and are off in the sta ndby mode. the out-to-ground fet is turned on whenever the fet_on bit is '0'. figure 26. analog and digital switches spk_r spk_l mic dp dm vbus rxd txd d+ d- sw2 sw1 sw3 sw4 sw6 sw7 sw5 vusb ldo m0 vinusb motg m1
analog integrated circuit device data ? 99 freescale semiconductor mc34708 functional bloc k description 7.8.4.8 audio type 1 operation mode audio type 1 accessories have the same interface shown in figure 27 , either stereo or mono, with or without a remote control, or with or without a microphone. when a device, such as a micr ophone is not connected to the accessory, the corresponding pin in the mini-usb connector will be left floating. with the normal operation setting of the control bits, the accessory is identi fied as an audio type 1 device, the analog switches sw4 and sw7 for spk_r to dp, spk_l to dm, and sw5 for vbus to mic are turned on, and the motg, and m0 switches are turned off, to isolate the vbus pin. the mc34708 supports the remote control key for an audio ty pe 1 device. if the raw data = 0, the adc is turned on periodically to monitor the id line change caused by the key press. the period is programmed by the device wake-up bits. if the adc result changes, the adc_change bit in the usb interrupt sense register is set to inform the baseband. if the raw data = 1, a comparator is enabled to monitor the key pr ess. the timing of the key press when raw data = 1 is shown in figure 28 . if a key is pressed for a time less than 20 ms, the mc34708 ignores it. if the key is still pressed after 20 ms, the mc34708 starts a timer to count the time during which the key is kept pressed. there are three conditions according to the pres s time: error key press, short key press, and long key press. 1. error key press: if the key press time is less than tkp, the error bit in the usb bu tton register and the short key press bit kp in usb interrupt sense register are se t to indicate that an error happens. the error bit is reset to '0' when the usb button register is read or the next key press happens. th e kp bit is cleared when the in terrupt 1 register is read. 2. short key press: if the key press time is between tkp an d tlkp, the kp bit and the corresponding button bit in usb button are set to inform the baseband. if the adc result is not one of the adc values of the 13 buttons, the unknown bit in the button 2 register is set. the int pin is driven high when the key is released and returns to low when the interrupt register is read. the kp bit is cleared when the usb interrupt sense register is read. 3. long key press: if the key press time is longer than tlkp, t he long key press bit lkp in the usb interrupt sense register, and the corresponding button bit, are set to inform the baseband. if the adc result is not o ne of the adc values of the 13 buttons, the unknown bit in the usb button register is set. when the key is released, the long key release bit lkr in the interrupt 2 register is set to interrupt the baseband again. figure 27. audio accessory with remote control and microphone table 93. switch configuration when controlled by the device type register device type audio usb uart usb chg dedicated chg on sw# 4, 5, 7 3, 6, 1, 2 3, 6 - off sw motg, m0 - (67) - - device type 5wt1 chg 5wt2 chg jig_usb_on jig_usb_off jig_uart_on jig_uart tty on sw# - - 3, 6 3, 6 4, 5, 7 off sw - - - (67) motg, m0 notes 67. switches m0, m1, and motg are controlled by software by the otgen and vusbsel bits.
analog integrated circuit device data ? freescale semiconductor 100 mc34708 functional block description figure 28. operation of the headset with remote control and microphone figure 29. remote control key press timing the id detection circuit continues to be on for detaching detection in the active mode, and samples the id line every interval programmed by the device wake-up bits in the usb timing register. when the id_float rising edge is detected, the detach bit in the usb interrupt sense register is set to inform the hos t the accessory is detached. th e mc34708 then enters standby mode. vbus id d+ d- gnd baseband shld adc id det audio accessory mic spkr_r spkr_l vbus dp dm id gnd ? 20ms key press 20ms t kp t lkp error int kp int lk p lkr int adc time button register read kp interrupt status 0 register kp bit written to a one interrupt status 0 register kp bit written to a one interrupt status 0 register lkp bit written to a one interrupt status 0 register lkr bit written to a one
analog integrated circuit device data ? 101 freescale semiconductor mc34708 functional bloc k description 7.8.4.9 jig cable usb and uart the jig cable is used for test and development and has an id re sistance to differentiate it from a regular usb cable. the jig cable has 2 id resistance values to resemble a usb jig type1/2 , and 2 id resistance values to resemble a uart jig type1/2 cable. 7.8.4.9.1 usb jig cable 1 or 2 under normal operation, setting the control bits when the identifi ed accessory is a usb jig 1 or 2 cable, both the dplus to dp, the dminus to dm swit ches are switched on. when sw_hold = 0, the switching action of dplus to dp, and t he dminus to dm switches are controlled by the wait bit. if wait = 1, the signal switches w ill be turned on after a wait. if wait = 0, the si gnal switches won't be turned on until the wai t bit is set to '1' by the spi/i 2 c. when sw_hold = 1, regardless of w hat the wait is set to, '0' or '1 ', the signal switches are turned on, once the usb jig cable is identified. the id detector and the vbus detector both m onitor the detachment of the usb jig cable. the id detection circuit continues to be on for detachment detection in the active mode. when the id_flo at is set, the detach bit in the interrupt status 0 register is set to inform the host. when the usbdets is set to '0', which means either the vbus power is removed or the cable is detached, the detach bit is also set to inform the host. the mini usb interface moves to the standby mode. if the detach bit is set, due to the removing only the vbus or the id resistance, and the cable is not detached completely, the identification flow will be triggered again. the id_float bit or usbdets bit still indicate that an accessory is connec ted when the mini usb interface moves to the standby mode. all the signal switches are turned off 7.8.4.9.2 uart jig cable 1 or 2 under normal operation, setting the control bits when the identifi ed accessory is a uart jig cable 1 or 2, both the rxd to dp and the txd to dm switches are switched on. when sw_hold = 0, the switching action of rxd to dp, and th e txd to dm switches, are cont rolled by the wait bit. if wait = 1, the signal switches will be turned on after a wait time. if wait = 0, the signal swit ches won't be turned on until the wait bit is set to '1' by the spi/i 2 c. when sw_hold = 1, regardless of what the wait is se t to, '0' or '1', the signal switches are turned on, once the uart jig cable is identified. the id detection comparator continues to be on for detachment detection in the acti ve mode. when the id_float is set, the detach bit in the interrupt status 0 register is set to inform the host that the accessory is detached. the mini usb interface then enters the standby mode. 7.8.4.10 tty operation mode a tty converter is a type of audio accessory. it has its own id re sistance. when a tty converter is attached, this sets the tty bit in the usb device type register and the attach interrupt bit in the interrupt status 0 register. during normal operation, w hen setting the control bits, the automatic switch configuration of the tty converter, is similar to that of an audio type 1 access ory. the spk_r to dp switch, and mic to vbus switch are turned on, but the spk_l to dm switch can only be turned on when tty_skpl bit in usb control register is manually set to 1. in ad dition, the motg, and m0 switches are turned off to isolate the vbus pin.the tty accessory doesn?t support the remote contro l key. the power save mode operation and the detachment detection are the same as those of the audio type 1 device. 7.8.4.11 uart operation mode during normal operation, when setting the control bits, when the identified accessory is a uart cable, both the rxd and the txd switches are switched on (see figure 30 ). the id detection comparator continues to be on for detachment detection in the acti ve mode. when the id_float is set, the detach bit in the usb interrupt sense register, is set to in form the host that the accessor y is detached. the mc34708 usb detection then enters standby mode.
analog integrated circuit device data ? freescale semiconductor 102 mc34708 functional block description figure 30. uart operation 7.8.4.12 usb host (pc or hub) operation mode when the attached accessory is a usb host or hub, the id pin floats. during normal operation, when setting the control bits, bo th the d plus to dp and the d minus to dm switches are switched on (see figure 31 ). the mini usb interface sets the charger input current limit and sets the bit usb in the usb device type register. when sw_hold = 0, the switching action of d+ to dp and t he d- to dm switches, are cont rolled by the wait bit. if wait = 1, the signal switches will be turned on after a wait time. if wait = 0, the signal swit ches won't be turned on until the wait bit is set to '1' by the spi. when sw_hold = 1, regardless of what the wa it is set to, '0' or '1', the signal switches are turned on o nce the usb host is identified. after the dplus to dp and the dminus to dm switches are turned on, the baseband can pull the dplus signal high to start the usb attaching sequence. the detachment is detected by the fallin g edge of the usbdets signal. when the usbdet s falls, the detach bit is set to inform the baseband. the mc34708 usb detection then enters the standby mode. figure 31. usb operation 7.8.4.13 usb charger or dedi cated charger operation mode when the attached accessory is a usb charger or dedicate d charger, the mc34708 enables the bit usb charge or the dedicated chg in the usb device type register. during normal operation when setting of the control bits, the d plus and d minus switches are turned on for the usb charger, but not for the dedicated charger. the vbus detector is used to monitor the detachment of the char ger. the falling edge of usbdets is an indication of charger detachment. unplugging the mini-u sb connector and unplugging the ac side, both lead to the same detachment conclusion. the detach bit is set to inform the host. the mc34708 usb detection then enters the standby mode. vbus id d+ d- gnd baseband shld uart cable rxd txd dp dm id gnd uart interface adc id det vbus det uart vbus ` vbus id d+ d- gnd baseband shld usb cable dplus dminus dp dm id gnd usb host adc id det vbus det 5v usb xcvr vbus
analog integrated circuit device data ? 103 freescale semiconductor mc34708 functional bloc k description 7.8.4.14 5-wire charger or a/v charger mode when the attached accessory is a 5-wire charger or a/v c harger, the mc34708 enables the appropriate device type 5.0 w chg or a/v in the usb device type register. the vbus detector is used to monitor the detac hment of the charger. the falling edge of usbdets is an indication of the charger detachment. both unplugging the mini-usb connector and unplugging the ac side lead to the same detachment conclusion. the detach bit is set to inform the host. then the mc34708 usb detection enters the standby mode. 7.8.4.15 charger input current limit setting when the manual sw_b bit is set to 1, the mc34708 automatically detects what device is attached. 7.8.4.16 unknown accessory operation mode when an unknown accessory is attached, the id_float bit is cleared or the usbdets bit is set to '1'. only the unknown_atta bit is set to interrupt the baseband. the attach bit is not set to distinguish the unknown accessory from the known accessory. no other actions are taken.the falling edge of the usbdets or the rising edge of the id_f loat signals can trigger the detachment detection. the detach bit is set to inform the detachment of the unknown accessory. the usb detection then enters the standby mode. 7.8.4.17 software reset the usb detection supports a software reset, which is realized by writing the reset bit in the usb control register to 1. the consequence of the software reset is the same as the hardware reset. all register bits reset by the mini-usb will be reset. 7.8.4.18 id resistance value assignment the id resistors used are standard 1% resistors. table 95 lists the complete 32 id resistor assignment. those with the assigned functions filled are ones that are already used with special functions. the ones reserv ed can be assigned to other functions. table 94. id detection thresholds uid pin external connection uid pin voltage (68) idfloats idgnds idfactorys accessory resistor to ground 0.18 * vcore < uid < 0.77 * vcore 0 1 0 non-usb accessory is attached (per cea-936-a spec) grounded 0 < uid < 0.12 * vcore 0 0 0 a type plug (usb default slave) is attached (per cea-936-a spec) floating 0.89 * vcore < uid < vcore 1 1 0 b type plug (usb host, otg default master or no device) is attached. voltage applied 3.6 v < uid (1) 1 1 1 factory mode notes 68. uid maximum voltage is 5.25 v table 95. id resistance assignment item# adc result id resistance k ? assignment 0 00000 <1.9 reserved 1 00001 2.0 s0 2 00010 2.604 s1 3 00011 3.208 s2 4 00100 4.014 s3
analog integrated circuit device data ? freescale semiconductor 104 mc34708 functional block description the remote control architecture is illustrated in figure 32 . the recommended resistors for the remote control resistor network are given in table 96 . figure 32. remote control architecture 5 00101 4.820 s4 6 00110 6.03 s5 7 00111 8.03 s6 8 01000 10.03 s7 9 01001 12.03 s8 10 01010 14.46 s9 11 01011 17.26 s10 12 01100 20.5 s11 13 01101 24.07 s12 14 01110 28.7 uart jig cable 2 15 01111 34.0 uart jig cable 1 16 10000 40.2 usb jig cable 2 17 10001 49.9 usb jig cable 1 18 10010 64.9 factory mode 19 10011 80.6 audio type 2 20 10100 102 ppd 21 10101 121 reserved 22 10110 150 uart 23 10111 200 5w type 1 24 11000 255 reserved 25 11001 301 reserved 26 11010 365 a/v 27 11011 442 5w type 2 28 11100 523 reserved 29 11101 619 tty 30 11110 1000 audio type 1 31 11111 - id float table 95. id resistance assignment item# adc result id resistance k ? assignment ? ?... r 1 r 2 r 3 r 13 r 14 hold gnd send / end / id
analog integrated circuit device data ? 105 freescale semiconductor mc34708 functional bloc k description 7.8.4.19 usb interface electrical specifications table 96. id remote control values resistor standard value k ? id resistance r1 2.0 2.0 r2 0.604 2.604 r3 0.604 3.208 r4 0.806 4.014 r5 0.806 4.82 r6 1.21 6.03 r7 2.0 8.03 r8 2.0 10.03 r9 2.0 12.03 r10 2.43 14.46 r11 2.8 17.26 r12 3.24 20.5 r13 3.57 24.07 r14 590/976 614/1000 table 97. usb interface elect rical characteristics characteristics noted under conditions bp = 3.6 v, v bus = 5.0 v, - 40 ? c ? t a ? 85 ? c, unless otherwise noted. typical values at bp = 3.6 v and t a = 25 c under nominal conditions, unless otherwise noted. symbol characteristic min typ max unit notes power input i dm detection module quiescent current ? in standby mode ? when accessory is attached & int_mask = ?1? ? in active mode (v dd < v bus ) ? in active mode (v dd < v bus ) - - - - 2 125 550 850 3 160 650 1000 ? a i vbus vbus supply quiescent current ? in vbus otg ? in active mode - audio or tty - - - - 1.5 0.5 ma accessory detect switch r spk_on r spk_onmct r spk_onflt spk_l and spk_r switches ? on resistance (20 hz to 470 khz) ? matching between channels ? on resistance flatness (from -1.2 to 1.2 v) - - - 30 3.0 0.3 - - - w r usb_on r usb_onmct r usb_onflt d+ and d- switches ? on resistance (0.0 hz to 240 mhz) ? matching between channels ? on resistance flatness (from 0.0 to 3.3 v) - - - 5.0 0.1 0.02 8.0 1.0 0.4 w
analog integrated circuit device data ? freescale semiconductor 106 mc34708 functional block description r uart_on r uart_onflt rxd and txd switches ? on resistance ? on resistance flatness (from 0.0 to 3.3 v) - - - - 60 6.0 w r mic_on mic switches ? on resistance (at 1.5 v mic bias voltage) - 75 150 w r pd_audio pull-down resistors between spk_l or spk_r pins to gnd - 100 - k ? signal voltage range ?mic ? spk_l, spk_r ? d+, d-, rxd, txd - -1.5 -0.3 - - - 1.5 1.5 3.6 v v a_psrr psrr - from bp (100 mvrms) to dp/dm pins ?20 hz to 20 khz with 32/16 ? load. - - -60 db t hd total harmonic distortions ?20 hz to 20 khz with 32/16 ? load. - - 0.05 % v a_ct crosstalk between two channels ?20 hz to 20 khz with 32/16 ? load. - - -50 db v a_iso off channel isolation ? less than 1.0 mhz - - -100 db power supply type identification v dat_src data source voltage ? loaded by 0~200 a 0.5 0.6 0.7 v i dat_src data source current 0.0 - 200 a v dat_ref data detect voltage 0.3 0.35 0.4 v v cr_ref car kit detect voltage 0.8 0.9 1.0 v i dat_sink data sink current ? dm pin is biased between 0.15 to 3.0 v 65 100 135 a c dp/dm dp, dm pin capacitance - 8.0 - pf r dp/dm dp, dm pin impedance ? all switches are off (switch_open = 0) - 50 - m ? id detection v float id float threshold ? detection threshold - 2.3 - v t id_float id float detection deglitch time - 20 - ms iid pull-up current source ? when adc result is 1xxxx ? when adc result is 0xxxx 1.9 30.4 2.0 32 2.1 33.6 a i vcbl v vcbl_l v vcbl_h video cable detection ? detection current ? detection voltage low threshold ? detection voltage high threshold 1.0 - - 1.2 50 118 1.4 - - ma mv mv table 97. usb interface el ectrical characteristics characteristics noted under conditions bp = 3.6 v, v bus = 5.0 v, - 40 ? c ? t a ? 85 ? c, unless otherwise noted. typical values at bp = 3.6 v and t a = 25 c under nominal conditions, unless otherwise noted. symbol characteristic min typ max unit notes
analog integrated circuit device data ? 107 freescale semiconductor mc34708 functional bloc k description 7.9 serial interfaces the ic contains a number of programmabl e registers for control and communication. the majority of registers are accessed through a spi interface in a typical application. the same register set may alternatively be accessed with an i 2 c interface that is muxed on spi pins. table 98 describes the muxed pin options for the spi and i 2 c interfaces; further details for each interface mode follow. 7.9.1 spi interface the ic contains a spi interface port which allows access by a pr ocessor to the register set. vi a these registers, the resources of the ic can be controlled. the registers also provide status information about how the ic is operating, as well as information o n external signals. because the spi interface pins can be reconfigured for reuse as an i 2 c interface, a configuration pr otocol mandates that the cs pin is held low during a turn on event for the ic (a weak pull-do wn is integrated on the cs pin) . the state of cs is latched in during the initialization phase of a cold st art sequence, ensuring that the i 2 c bus is configured before the interface is activated. with the cs pin held low during startup (as would be the case if conne cted to the cs driver of an unpowered processor due to the integrated pull down), then the bus configuration will be latched for spi mode. the spi port utilizes 32-bit serial data words comprised of 1 write/read_b bit, 6 address bits, 1 null bit, and 24 data bits. t he addressable register map spans 64 registers of 24 data bits each. the map is not fu lly populated, but it follows the legacy conventions for bit positions corresponding to common functionality with previous generation fsl products. 7.9.1.1 spi interface description for a spi read, the first bit sent to the ic must be a zero indicati ng a spi read cycle. next, the six bit add ress is sent msb first. this is followed by one dead bit to allow for more address decode time. the mc34708 will clock the above bits in on the rising edge of the spi clock. the 24 data bits are then driven out on the miso pin on the falling edge of the spi clock, so the master can clock them in on the rising edge of the spi clock. for each mosi spi transfer, first a one is written to the write/read_b bit if this spi transfer is to be a write. a zero is wri tten to the write/read_b bit if this is to be a read co mmand. if a zero is written, then any data sent after the address bits are ignored a nd the internal contents of the field addressed do not change when the 32nd clk is sent. t vcbl video cable detection time (video c able detection current source on time) - 20 - ms t rmtcon_dg key press comparator debounce time - 20 - ms table 98. spi / i 2 c bus configuration pin name spi mode functionality i 2 c mode functionality cs configuration (69) , chip select configuration (70) clk spi clock scl: i 2 c bus clock miso master in, slave out (data output) sda: bi-directional serial data line mosi master out, slave in (data input) a0 address selection (71) notes 69. cs held low at cold start, configures the interface for spi mode; once activated, cs functi ons as the spi chip select. 70. cs tied to vcoredig at cold st art, configures the interface for i 2 c mode; the pin is not used in i 2 c mode, other than for configuration. 71. in i 2 c mode, the mosi pin is hardwired to ground, or vcor edig is used to select bet ween two possible addresses. table 97. usb interface el ectrical characteristics characteristics noted under conditions bp = 3.6 v, v bus = 5.0 v, - 40 ? c ? t a ? 85 ? c, unless otherwise noted. typical values at bp = 3.6 v and t a = 25 c under nominal conditions, unless otherwise noted. symbol characteristic min typ max unit notes
analog integrated circuit device data ? freescale semiconductor 108 mc34708 functional block description for a spi write, the first bit sent to the mc34708 must be a one, indicating a spi write cycle. next the six bit address is sen t msb first. this is followed by one dead bit to allow for more address decode time. the data is then sent msb first. the spi data is written to the spi register wh ose address was sent at the start of the spi cycle on the falling edge of the 32nd spi clock. additionally, whe never a spi write cycle is taking plac e the spi read data is shifted out fo r the same address as for the write cycle. next the 6-bit address is written, msb first. finally, data bits are written, msb first. once all the data bits are writ ten then the data is transferred into the actual registers on the falling edge of the 32nd clk. the cs polarity is active high. the cs line must remain high during the entire spi transfer. for a write sequence it is possibl e for the written data to be corrupted, if afte r the falling edge of the 32nd clock the cs goes low before it's required time. cs can go low before this point and the spi transaction will be ignored, but after that point the write process is started and cannot be stopped, because the write strobe pulse is already being generated, and cs going low may cause a runt pulse that may or may not be wide enough to clock all 24 data bits properly. to start a new spi transfer, the cs line must be toggled low and then pu lled high again. the miso line will be tri-stated while cs is low. the register map includes bits that are r ead/write, read only, read/write ?1? to clea r (i.e., interrupts), and clear on read, r eserved, and unused. refer to the spi/i2c register map and the individual subcircuit descriptions to determine the read/write capability of each bit. all unused spi bits in each register must be wr itten to as zeroes. a spi read back of the address field and unused bits are returned as zeroes. to read a fiel d of data, the miso pin will output the data field pointed to by the 6 address bits loaded at the beginning of the spi sequence. figure 33. spi transfer prot ocol single read/write access figure 34. spi transfer protocol multiple read/write access ? cs clk mosi miso write_en a ddress5 a dd r e ss 4 a ddress3 a ddress2 a ddress 1 a ddress 0 data 23 data 1 data 0 data 23 data 1 data 0 d ata 22 d ata 22 ?d ead bit? ? 24 bits data 24 bits data 24 bits data 24 bits data pr ea mble first address preamble another address mosi miso cs
analog integrated circuit device data ? 109 freescale semiconductor mc34708 functional bloc k description 7.9.1.2 spi timing requirements the following diagram and table summarize the spi timing requirem ents. the spi input and output levels are set via the spivcc pin, by connecting it to the desired supply. this wo uld typically be tied to sw5 and programmed for 1.80 v. the strength of the miso driver is programmable through the spidrv [1:0] bits. see thermal protection thresholds for detailed spi electrical characteristics. figure 35. spi interface timing diagram table 99. spi interface timing specifications (72) parameter description t min (ns) t selsu time cs has to be high before the first rising edge of clk 15 t selhld time cs has to remain high after the last falling edge of clk 15 t sellow time cs has to remain low between two transfers 15 t clkper clock period of clk 38 t clkhigh part of the clock period w here clk has to remain high 15 t clklow part of the clock period where clk has to remain low 15 t wrtsu time mosi has to be stable bef ore the next rising edge of clk 4.0 t wrthld time mosi has to remain stable after the rising edge of clk 4.0 t rdsu time miso will be stable before the next rising edge of clk 4.0 t rdhld time miso will remain stable after the falling edge of clk 4.0 t rden time miso needs to become active after the rising edge of cs 4.0 t rddis time miso needs to become inacti ve after the falling edge of cs 4.0 notes 72. this table reflects a maxi mum spi clock frequency of 26 mhz. cs clk mosi miso t clkper t clklow t dkhigh t selsu t selhld t sellow t rddis t rdhld t rdsu t rden t wrtsu t wrthld
analog integrated circuit device data ? freescale semiconductor 110 mc34708 functional block description 7.9.2 i 2 c interface 7.9.2.1 i 2 c configuration when configured for i 2 c mode, the interface may be used to access the co mplete register map previously described for spi access. since spi configuration is more typical, references wit hin this document will generally refer to the common register se t as a ?spi map? and bits as ?spi bits?; howeve r, it should be understood that access reverts to i 2 c mode when configured as such. the spi pins clk and miso are reused for the scl and sda lines respectively. selection of i 2 c mode for the interface is configured by hard-wiring the cs pin to vc oredig on the application board. the state of cs is latched in during the initializat ion phase of a cold start sequence, so the i 2 cs bit is defined for bus configuration before the interface is activated. the pull-down on cs will be deactivated if the hi gh state is detec ted (indicating i 2 c mode). in i 2 c mode, the miso pin is connected to the bus as an open drain driver, and the logic level is set by an external pull-up. the part can function only as an i 2 c slave device, not as a host. 7.9.2.2 i 2 c device id i 2 c interface protocol requires a device id for addressing the targ et ic on a multi-device bus. to allow flexibility in addressin g for bus conflict avoidance, pin programmable selection is provided to allow configurat ion for the address lsb(s). this product supports 7-bit addressing only; support is not provided for 10-bit or general call addressing. because the mosi pin is not utilized for i 2 c communication, it is reassigned for pin programmable address selection by hardwiring to vcoredig or gnd at th e board level when configured for i 2 c mode. mosi will act as bit 0 of the address. the i 2 c address assigned to fsl pm ics (shared amongst our portfolio) is given as follows: 00010-a1-a0, the a1 and a0 bits are allowed to be configured for ei ther 1 or 0. the a1 address bit is internally hardwired as a ?0?, leaving the lsb a0 for board level configuration. the designated address then is defined as: 000100-a0. 7.9.2.3 i 2 c operation the i 2 c mode of the interface is implemented generally follo wing the fast mode definition which supports up to 400 kbits/s operation. (exceptions to the standard are noted to be 7-bit only addressing, and no support for general call addressing) timin g diagrams, electrical specificat ions, and further details on this bus standard, is available on the internet, by typing ? ?i 2 c specification? in the web search string field. standard i 2 c protocol utilizes bytes of 8 bits, with an acknowledge bit (ack) required between each byte. however, the number of bytes per transfer is unrestricted. the r egister map is organized in 24 bit registers which corresponds to the 24 bit words supported by the spi protocol of this product. to ensure that i 2 c operation mimics spi transactions in behavior of a complete 24 bit word being written in one transaction, software is expected to perform write transactions to the device in 3-byte sequences , beginning with the msb. internally, data latc hing will be gated by the acknowledge at the completion of writing the third consecutive byte. failure to complete a 3-byte write sequence will abort the i 2 c transaction and the register will reta in its previous value. this could be due to a premature stop command from the master, for example. i 2 c read operations are also performed in byte increments sepa rated by an ack. read operations also begin with the msb and 3-bytes will be sent out unless a stop command or nack is received prior to completion. the following examples show how to write and read data to the ic. the host initiates and terminates all communication. the host sends a master command packet after drivi ng the start condition. the device will respond to the host if the master command packet contains the corresponding slave addres s. in the following examples, the device is shown always responding with an ack to transmissions from the host. if at any time a nak is rece ived, the host should terminate th e current transaction and retry t he transaction.
analog integrated circuit device data ? 111 freescale semiconductor mc34708 functional bloc k description figure 36. i 2 c 3-byte write example figure 37. i 2 c 3-byte read example ? device address r egi s ter addr es s packet type start r/w host sda (to mi so) a c k slave sda (from miso) a c k master driven data (byte 2) master driven data (byte 1) master driven data (byte 0) 16 23 0 7 8 15 stop host can also drive another start instead of stop a c k a c k a c k packet type 0 0 7 0 0 7 0 host sda (to miso) slave sda (from miso) continuation ? device ad dr e ss r egi ster addr ess device address packet type star t 0 0 r/w 16 23 8 15 16 23 0 7 8 15 a c k stop a c k a c k start 0 7 r/w a c k a c k na ck ap li te d r i ven d ata (byte 2) packet type ap lite driven data (byte 1) ap lite driven data (byte 0) host can also drive another start instead of stop 0 1 host sda (to miso) slave sda ( from miso) host sda (to miso) slave sda (from miso) continuation pmic driven data pmic driven data pmic driven data
analog integrated circuit device data ? freescale semiconductor 112 mc34708 functional block description 7.9.3 spi/i 2 c specification 7.10 configuration registers 7.10.1 register set structure the general structure of the register set is given in the following table. expanded bit descriptions are included in the follow ing functional sections for application guidance. for brevity?s sake, references are occasionally made herein to the register set a s the ?spi map? or ?spi bits?, but note that bit access is also possible through the i 2 c interface option so such references are implied as generically applicable to the register set accessible by either interface. table 100. spi/i 2 c electrical characteristics characteristics noted under conditions bp = 3.6 v, v bus = 5.0 v, - 40 ? c ? t a ? 85 ? c, unless otherwise noted. typical values at bp = 3.6 v and t a = 25 c under nominal conditions, unless otherwise noted. symbol characteristic min typ max unit notes spi interface logic io v incslo input low cs 0.0 - 0.4 v v incshi input high cs 1.1 - spivcc+0.3 v v inmosilo / v inclklo input low, mosi, clk 0.0 - 0.3*spivcc v v inmosihi / v inclkhi input high, mosi, clk 0.7*spivcc - spivcc+0.3 v v misolo / v intlo output low miso, int ? output sink 100 ? a 0.0 - 0.2 v v misohi / v inthi output high miso, int ? output source 100 ? a spivcc-0.2 - spivcc v v cc-spi spivcc operating range 1.75 - 3.6 v t misoet miso rise and fall time, cl = 50 pf, spivcc = 1.8 v ?spidrv [1:0] = 00 ?spidrv [1:0] = 01 (default) ?spidrv [1:0] = 10 ?spidrv [1:0] = 11 - - - - 6.0 2.5 3.0 2.0 - - - - ns table 101. register set register register register register 0 interrupt status 0 16 memory a 32 regulator mode 0 48 adc5 1 interrupt mask 0 17 memory b 33 gpiolv0 control 49 adc6 2 interrupt sense 0 18 memory c 34 gpiolv1 control 50 adc7 3 interrupt status 1 19 memory c 35 gpiolv2 control 51 input monitoring 4 interrupt mask 1 20 rtc time 36 gpiolv3 control 52 supply debounce 5 interrupt sense 1 21 rtc alarm 37 usb timing 53 vbus monitoring 6 power up mode sense 22 rtc day 38 usb button 54 led control 7 identification 23 rtc day alarm 39 usb control 55 pwm control 8 regulator fault sense 24 regulator 1 a/b voltage 40 usb device type 56 unused
analog integrated circuit device data ? 113 freescale semiconductor mc34708 functional bloc k description 7.10.2 specific registers 7.10.2.1 ic and version identification the ic and other version details can be read via the identific ation bits. these are hardwired on the chip and described in table 102 . 7.10.2.2 embedded memory there are four register banks of general purpose embedded memory to store critical data. the data written to mema[23:0], memb[23:0], memc[23:0], and memd[23: 0] is maintained by the coin cell when the main battery is deeply discharged, removed, or contact-bounced (i.e., during a power cut). the contents of the embedded memory are reset by rtcporb. a known pattern can be maintained in these registers to validate confidence in the rtc contents when power is restored after a power cut event. alternatively, the banks can be used for any system need for bit retenti on with coin cell backup. 9 reserved 25 regulator 2 & 3 voltage 41 unused 57 unused 10 reserved 26 regulator 4 a/b voltage 42 unused 58 unused 11 reserved 27 regulator 5 voltage 43 adc 0 59 unused 12 unused 28 regulator 1 & 2 mode 44 adc 1 60 unused 13 power control 0 29 regulator 3, 4 and 5 mode 45 adc 2 61 unused 14 power control 1 30 regulator setting 0 46 adc 3 62 unused 15 power control 2 31 swbst control 47 adc4 63 unused table 102. ic revision bit assignment identifier value purpose full_layer_rev[2:0] xxx represents the full layer revision ? pass 2.4 = 010 metal_layer_rev[2:0] xxx represents the metal layer revision ? pass 2.4 = 100 fin[2:0] 000 fin version ? pass 2.4 = 000 fab[2:0] 000 fab version ? pass 2.4 = 000 table 101. register set register register register register
analog integrated circuit device data ? freescale semiconductor 114 mc34708 functional block description 7.10.3 spi/i 2 c register map the complete spi bitmap is given in table 103 . table 103. spi/i 2 c register map legend register types register values reset r/w read / write 0 = low bits loaded at cold start based on pums value r/wm read / write modify 1 = high bits reset by por or global reset w1c write one to clear x = variable resetb / bits reset by por or global ro read only bits reset by rtcporb or global reset nu not used bits reset by por or offb bits reset by rtcporb only musbrst table 104. spi/i 2 c register map address register name type default mc34708 spi register map 0 interrupt status 0 table 105 w1c h00_00_00 23 22 21 20 19 18 17 16 stuck_key_rcv stuck_key adc_change unknown_ atta lkr lkp kp detach 15 14 13 12 11 10 9 8 attach - lowbatt - - - - - 7 6 5 4 3 2 1 0 - - usbovp - usbdet tspendet tsdonei adcdonei 1 interrupt mask 0 table 106 r/w hff_ff_ff 23 22 21 20 19 18 17 16 stuck_key_rcv_ m stuck_key_m adc_change_ m unknown_ atta_m lkr_m lkp_m kp_m detach_m 15 14 13 12 11 10 9 8 attach_m - lowbattm - - - - - 7 6 5 4 3 2 1 0 - - usbovpm - usbdetm tspendetm tsdonem adcdonem 2 interrupt sense 0 table 107 ro h00_00_00 23 22 21 20 19 18 17 16 - - musb_adc_ status id_gnds id_floats id_det_ends vbus_det_ ends - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - usbovps - usbdets - - - 3 interrupt status 1 table 108 w1c h00_00_00 23 22 21 20 19 18 17 16 - - - gpiolv3i gpiolv2i gpiolv1i gpiolv0i scpi 15 14 13 12 11 10 9 8 clki therm130 therm125 therm120 therm110 memhldi warmi pci 7 6 5 4 3 2 1 0 rtcrsti sysrsti wdiresti pwron2i pwron1i - todai 1hzi 4 interrupt mask 1 table 109 r/w h5f_77_fb 23 22 21 20 19 18 17 16 - - - gpiolv3m gpiolv2m gpiolv1m gpiolv0m scpm 15 14 13 12 11 10 9 8 clkm therm130m therm125m therm120m therm110m memhldm warmm pcm 7 6 5 4 3 2 1 0 rtcrstm sysrstm wdirestm pwron2m pwron1m - todam 1hzm
analog integrated circuit device data ? 115 freescale semiconductor mc34708 functional bloc k description 5 interrupt sense 1 table 110 ro hxx_xx_xx 23 22 21 20 19 18 17 16 - - - gpiolv3s gpiolv2s gpiolv1s gpiolv0s - 15 14 13 12 11 10 9 8 clks therm130s therm125s therm120s therm110s - - - 7 6 5 4 3 2 1 0 - - - pwron2s pwron1s - - - 6 power up mode sense table 111 ro h00_00_xx 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - pums5s pums4s pums3s pums2s pums1s ictests 7 identification table 112 rw h00_00_08 23 22 21 20 19 18 17 16 page[4:0] - - - 15 14 13 12 11 10 9 8 - - - - fab[2:0] fin[2] 7 6 5 4 3 2 1 0 fin[1:0] full_layer_rev[2:0] metal_layer_rev[2:0] 8 regulator fault sense table 113 rw h00_xx_xx 23 22 21 20 19 18 17 16 regscpen - - - - - - - 15 14 13 12 11 10 9 8 - - - vgen2fault vgen1fault vdacfault vusb2fault vusbfault 7 6 5 4 3 2 1 0 swbstfault sw5fault sw4bfault sw4afault sw3fault sw2fault rsvd sw1fault 9-11 reserved nu hxx_xx_xx 23 22 21 20 19 18 17 16 - 15 14 13 12 11 10 9 8 - 7 6 5 4 3 2 1 0 - - - - - - - 12 unused nu h00_00_00 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - - 13 power control 0 table 118 r/w h00_00_40 23 22 21 20 19 18 17 16 coinchen vcoin[2:0] - - - 15 14 13 12 11 10 9 8 - - - - - - pcutexpb - 7 6 5 4 3 2 1 0 - clk32kmcuen useroffclk drm useroffspi warmen pccounten pcen 14 power control 1 table 119 r/w h00_00_00 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 pcmaxcnt[3:0] pccount[3:0] 7 6 5 4 3 2 1 0 pct[7:0] table 104. spi/i 2 c register map
analog integrated circuit device data ? freescale semiconductor 116 mc34708 functional block description 15 power control 2 table 120 r/w h40_03_00 23 22 21 20 19 18 17 16 stbydly[1:0] on_stby_lp - - clkdrv[1:0] - 15 14 13 12 11 10 9 8 - spidrv[1:0] wdireset - standbyinv glbrsttmr[1:0] 7 6 5 4 3 2 1 0 pwron2dbnc[1:0] pwron1bdbnc[1:0] - pwron2 rsten pwron1rsten restarten 16 memory a table 121 r/w h00_00_00 23 22 21 20 19 18 17 16 mema[23:16] 15 14 13 12 11 10 9 8 mema[15:8] 7 6 5 4 3 2 1 0 mema[7:0] 17 memory b table 122 r/w h00_00_00 23 22 21 20 19 18 17 16 memb[23:16] 15 14 13 12 11 10 9 8 memb[15:8] 7 6 5 4 3 2 1 0 memb[7:0] 18 memory c table 123 r/w h00_00_00 23 22 21 20 19 18 17 16 memc[23:16] 15 14 13 12 11 10 9 8 memc[15:8] 7 6 5 4 3 2 1 0 memc[7:0] 19 memory d table 124 r/w h00_00_00 23 22 21 20 19 18 17 16 memd[23:16] 15 14 13 12 11 10 9 8 memd[15:8] 7 6 5 4 3 2 1 0 memd[7:0] 20 rtc time table 125 r/w h00_00_00 23 22 21 20 19 18 17 16 rtccalmode[1:0] rtccal[4:0] tod[16] 15 14 13 12 11 10 9 8 tod[15:8] 7 6 5 4 3 2 1 0 tod[7:0] 21 rtc alarm table 126 r/w h01_ff_ff 23 22 21 20 19 18 17 16 rtcdis spare spare spare spare spare spare toda[16] 15 14 13 12 11 10 9 8 toda[15:8] 7 6 5 4 3 2 1 0 toda[7:0] 22 rtc day table 127 r/w h00_00_00 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - day[14:8] 7 6 5 4 3 2 1 0 day[7:0] table 104. spi/i 2 c register map
analog integrated circuit device data ? 117 freescale semiconductor mc34708 functional bloc k description 23 rtc day alarm table 128 r/w h00_7f_ff 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - daya[14:8] 7 6 5 4 3 2 1 0 daya[7:0] 24 regulator 1a/b voltage table 129 r/wm hxx_xx_xx 23 22 21 20 19 18 17 16 rsvd[5:0] rsvd[5:4] 15 14 13 12 11 10 9 8 rsvd[3:0] sw1astby[5:2] 7 6 5 4 3 2 1 0 sw1astby[1:0] sw1a[5:0] 25 regulator 2&3 voltage table 130 r/wm hxx_xx_xx 23 22 21 20 19 18 17 16 - sw3stby[4:0] - sw3[4] 15 14 13 12 11 10 9 8 sw3[3:0] sw2stby[5:2] 7 6 5 4 3 2 1 0 sw2stby[1:0] sw2[5:0] 26 regulator 4 voltage table 131 r/wm hxx_xx_xx 23 22 21 20 19 18 17 16 sw4bhi[1:0] sw4bstby[4:0] sw4b[4] 15 14 13 12 11 10 9 8 sw4b[3:0] sw4ahi[1:0] sw4astby[4:3] 7 6 5 4 3 2 1 0 sw4astby[2:0] sw4a[4:0] 27 regulator 5 voltage table 132 r/wm h00_xx_xx 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - sw5tby[4:0] - - 7 6 5 4 3 2 1 0 - - - sw5[4:0] 28 regulator 1, 2 mode table 133 r/w hex_xx_8x 23 22 21 20 19 18 17 16 pllx pllen sw2dvsspeed[1:0] sw2uomode sw2mhmode sw2mode[3:2] 15 14 13 12 11 10 9 8 sw2mode[1:0] - - - - - - 7 6 5 4 3 2 1 0 sw1dvsspeed[1:0] sw1auomode sw1amhmode sw1amode[3:0] 29 regulator 3, 4, 5 mode table 134 r/w hxx_xx_xx 23 22 21 20 19 18 17 16 sw5uomode sw5mhmode sw5mode[3:0] sw4buomode sw4bmhmode 15 14 13 12 11 10 9 8 sw4bmode[3:0] sw4auomode sw4amhmode sw4amode[3:2] 7 6 5 4 3 2 1 0 sw4amode[1:0] sw3uomode sw3mhmode sw3mode[3:0] 30 regulator setting 0 table 135 r/wm h00_xx_xx 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - vusb2[1:0] vpll[1:0] vgen2[2] 7 6 5 4 3 2 1 0 vgen2[1:0] vdac[1:0] - vgen1[2:0] table 104. spi/i 2 c register map
analog integrated circuit device data ? freescale semiconductor 118 mc34708 functional block description 31 swbst control table 136 r/wm h00_00_xx 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 spare swbststbymode[1:0] spare swbstmode[1:0] swbst[1:0] 32 regulator mode 0 table 137 r/wm h0x_xx_xx 23 22 21 20 19 18 17 16 - - - vusb2mode vusb2stby vusb2en vusb2config vpllstby 15 14 13 12 11 10 9 8 vpllen vgen2mode vgen2stby vgen2en vgen2config vrefddren - - 7 6 5 4 3 2 1 0 rsvd vdacmode vdacstby vdacen vusben vusbsel vgen1stby vgen1en 33 gpiolv0 control table 138 r/w h00_18_0a 23 22 21 20 19 18 17 16 - - - - - - - spare 15 14 13 12 11 10 9 8 sre1 sre0 pus1 pus0 pue dse ode pke 7 6 5 4 3 2 1 0 int1 int0 dbnc1 dbnc0 hys dout din dir 34 gpiolv1 control table 139 r/w h00_18_0a 23 22 21 20 19 18 17 16 - - - - - - - spare 15 14 13 12 11 10 9 8 sre1 sre0 pus1 pus0 pue dse ode pke 7 6 5 4 3 2 1 0 int1 int0 dbnc1 dbnc0 hys dout din dir 35 gpiolv2 control table 140 r/w h00_18_0a 23 22 21 20 19 18 17 16 - - - - - - - spare 15 14 13 12 11 10 9 8 sre1 sre0 pus1 pus0 pue dse ode pke 7 6 5 4 3 2 1 0 int1 int0 dbnc1 dbnc0 hys dout din dir 36 gpiolv3 control table 141 r/w h00_18_0a 23 22 21 20 19 18 17 16 - - - - - - - spare 15 14 13 12 11 10 9 8 sre1 sre0 pus1 pus0 pue dse ode pke 7 6 5 4 3 2 1 0 int1 int0 dbnc1 dbnc0 hys dout din dir 37 usb timing table 142 r/w hxx_xx_xx 23 22 21 20 19 18 17 16 readvalid - - - td[3:0] 15 14 13 12 11 10 9 8 switching_wait[3:0] long_key_press[3:0] 7 6 5 4 3 2 1 0 key_press[3:0] device_wake_up[3:0] 38 usb button table 143 r/c hxx_xx_xx 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - unknown error s12 s11 s10 s9 s8 7 6 5 4 3 2 1 0 s7 s6 s5 s4 s3 s2 s1 s0 table 104. spi/i 2 c register map
analog integrated circuit device data ? 119 freescale semiconductor mc34708 functional bloc k description 39 usb control table 144 r/w hxx_xx_xx 23 22 21 20 19 18 17 16 readvalid dm_switching[2:0] dp_switching[2:0] vbus_switchin g[1] 15 14 13 12 11 10 9 8 vbus_switching[ 0] - sw_hold - - votgen clk_rst 7 6 5 4 3 2 1 0 active rst tty_spkl reset switch_open rawdata manual_sw_b wait 40 usb device type table 145 r hxx_xx_xx 23 22 21 20 19 18 17 16 usb_adc_id_results[4:0] - ukn_device id_factory 15 14 13 12 11 10 9 8 uartjig2 uartjig1 usbjig2 usbjig1 avchrg a/v tty ppd 7 6 5 4 3 2 1 0 usb otg dedicated_ chg usb chg 5w chg uart usb audio_type_2 audio_type_1 41 to 42 unused nu h00_00_00 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - - 43 adc 0 table 147 r/w h00_00_00 23 22 21 20 19 18 17 16 spare spare spare tspendeten spare tsstop[2:0] 15 14 13 12 11 10 9 8 tshold tscont tsstart tsen spare spare dietemp_en therm 7 6 5 4 3 2 1 0 spare adstop[2:0] adhold adcont adstart aden 44 adc 1 table 148 r/w h00_00_00 23 22 21 20 19 18 17 16 tsdly3[3:0] tsdly2[3:0] 15 14 13 12 11 10 9 8 tsdly1[3:0] addly3[3:0] 7 6 5 4 3 2 1 0 addly2[3:0] addly1[3:0] 45 adc 2 table 149 r/w h00_00_00 23 22 21 20 19 18 17 16 adsel5[3:0] adsel4[3:0] 15 14 13 12 11 10 9 8 adsel3[3:0] adsel2[3:0] 7 6 5 4 3 2 1 0 adsel1[3:0] adsel0[3:0] 46 adc 3 table 150 r/w h00_00_00 23 22 21 20 19 18 17 16 tssel7[1:0] tssel6[1:0] tssel5[1:0] tssel4[1:0] 15 14 13 12 11 10 9 8 tssel3[1:0] tssel2[1:0] tssel1[1:0] tssel0[1:0] 7 6 5 4 3 2 1 0 adsel7[3:0] adsel6[3:0] table 104. spi/i 2 c register map
analog integrated circuit device data ? freescale semiconductor 120 mc34708 functional block description 47 adc 4 table 151 r/w h00_00_00 23 22 21 20 19 18 17 16 adresult1[9:2] 15 14 13 12 11 10 9 8 adresult1[1:0] - - adresult0[9:6] 7 6 5 4 3 2 1 0 adresult0[5:0] - - 48 adc 5 table 152 r/w h00_00_00 23 22 21 20 19 18 17 16 adresult3[9:2] 15 14 13 12 11 10 9 8 adresult3[1:0] - - adresult2[9:6] 7 6 5 4 3 2 1 0 adresult2[5:0] - - 49 adc 6 table 153 r/w h00_00_00 23 22 21 20 19 18 17 16 adresult5[9:2] 15 14 13 12 11 10 9 8 adresult5[1:0] - - adresult4[9:6] 7 6 5 4 3 2 1 0 adresult4[5:0] - - 50 adc 7 table 154 r/w h00_00_00 23 22 21 20 19 18 17 16 adresult7[9:2] 15 14 13 12 11 10 9 8 adresult7[9:2] - - adresult6[9:6] 7 6 5 4 3 2 1 0 adresult6[5:0] - - 51 input monitoring table 155 r/w h01_31_7e 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 11 10 9 8 - - 7 6 5 4 3 2 1 0 - lowbatt[1:0] chren - - 52 supply debounce table 156 r/w h00_03_fd 23 22 21 20 19 18 17 16 - - - - - die_temp_db[1:0] 15 14 13 12 11 10 9 8 sup_ovp_db[1:0] - chrgled ovrd - 7 6 5 4 3 2 1 0 - vbusdb[1:0] vbattdb[1:0] - 53 vbus monitoring table 157 r/w hc0_36_1b 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 11 10 9 8 - - - - 7 6 5 4 3 2 1 0 - vbusth[2:0] vbustl[2:0] table 104. spi/i 2 c register map
analog integrated circuit device data ? 121 freescale semiconductor mc34708 functional bloc k description 54 led control table 158 r/w h60_06_00 23 22 21 20 19 18 17 16 chrgledgen chrgledg[1:0] chrgledgdc[5:1] 15 14 13 12 11 10 9 8 chrgledgdc[0] chrgledg ramp ledgper[1:0] chrgledren chrgledr[1:0] chrgledrdc[5] 7 6 5 4 3 2 1 0 chrgledrdc[4:0] chrgledr ramp chrgledrper[1:0] 55 pwm control table 159 r/w h00_00_00 23 22 21 20 19 18 17 16 pwm2clkdiv[5:0] pwm2duty[5:4] 15 14 13 12 11 10 9 8 pwm2duty[3:0] pwm1clkdiv[5:2] 7 6 5 4 3 2 1 0 pwm1clkdiv[1:0] pwm1duty[5:0] 56 to 63 unused nu h00_00_00 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - - table 104. spi/i 2 c register map
analog integrated circuit device data ? freescale semiconductor 122 mc34708 functional block description 7.10.4 spi register?s bit description table 105. register 0, interrupt status 0 name bit # r/w reset default description adcdonei 0 rw1c resetb 0x0 adc has finished requested conversions tsdonei 1 rw1c resetb 0x0 touchscreen has finish ed requested conversions tspendet 2 rw1c resetb 0x0 touch screen pen detection usbdet 3 rw1c offb 0x0 usb detect reserved 4 rw1c none 0x0 reserved usbovp 5 rw1c resetb 0x0 usb over voltage protection reserved 12:6 rw1c none 0x0 reserved lowbatt 13 rw1c resetb 0x0 low battery threshold warning reserved 14 rw1c none 0x0 reserved attach 15 rw1c musbrstb 0x0 1: accessory attached detach 16 rw1c musbrstb 0x0 1: accessory detached kp 17 rw1c musbrstb 0x0 1: remote controller key is pressed lkp 18 rw1c musbrstb 0x0 1: remote controller long key is pressed lkr 19 rw1c musbrstb 0x0 1: remote controller long key is released unknown_atta 20 rw1c musbrstb 0x0 1: an unknown accessory is attached adc_change 21 rw1c musbrstb 0x0 1: adc result has changed when the raw data = 0 stuck_key 22 rw1c musbrstb 0x0 1: stuck key is detected stuck_key_rcv 23 rw1c musbrstb 0x0 1: stuck key is recovered table 106. interrupt mask 0 name bit # r/w reset default description adcdonem 0 r/w resetb 0x1 adcdonei mask bit tsdonem 1 r/w resetb 0x1 tsdonei mask bit tspendetm 2 r/w resetb 0x1 touch screen pen detect mask bit usbdetm 3 r/w offb 0x1 usbdet mask bit reserved 4 r/w none 0x0 reserved usbovpm 5 r/w resetb 0x0 usb over voltage protection reserved 12:6 r/w none 0x0 reserved lowbattm 13 r/w resetb 0x1 lobatli mask bit reserved 14 rw1c none 0x0 reserved attach_m 15 r/w resetb 0x1 detach mask bit detach_m 16 r/w resetb 0x1 kp mask bit kp_m 17 r/w resetb 0x1 lkp mask bit lkp_m 18 r/w resetb 0x1 lkr mask bit lkr_m 19 r/w resetb 0x1 detach mask bit uknown_atta_m 20 r/w resetb 0x1 unknown_atta mask bit
analog integrated circuit device data ? 123 freescale semiconductor mc34708 functional bloc k description adc_change_m 21 r/w resetb 0x1 vbus power supply type ident ification completed mask stuck_key_m 22 r/w resetb 0x1 id resistance detection finished mask stuck_key_rcv_m 23 r/w resetb 0x1 for future use table 107. register 2, interrupt sense 0 name bit # r/w reset default description unused 2-0 r 0x0 not available usbdets 3 r none s usbdet sense bit reserved 4 r none 0x0 reserved usbovps 5 r none s usbovp sense bit reserved 6 r none 0x0 reserved unused 7 r none 0x0 not available reserved 9:8 r none 0x0 reserved unused 16-10 r 0x0 not available vbus_det_ends 17 r musbrstb 0x0 vbus power supply type identific ation completed sense bit id_det_ends 18 r musbrstb 0x0 id resistance detecti on finished sense bit id_floats 19 r none s id float sense bit id_gnds 20 r musbrstb 0x0 id ground sense bit 0: no 1: yes musb_adc_status 21 r none x mini usb adc conversion status 1: adc conversion completed 0: adc conversion in progress unused 23-22 r 0x0 not available table 108. register 3, interrupt status 1 name bit # r/w reset default description 1hzi 0 rw1c rtcporb 0x0 1.0 hz time tick todai 1 rw1c rtcporb 0x0 time of day alarm unused 2 r 0x0 not available pwron1i 3 rw1c offb 0x0 pwron1 event pwron2i 4 rw1c offb 0x0 pwron2 event wdireseti 5 rw1c rtcporb 0x0 wdi system reset event sysrsti 6 rw1c rtcporb 0x0 pwron system reset event rtcrsti 7 rw1c rtcporb 0x1 rtc reset event pci 8 rw1c offb 0x0 power cut event warmi 9 rw1c rtcporb 0x0 warm start event memhldi 10 rw1c rtcporb 0x0 memory hold event therm110 11 rw1c resetb 0x0 110 c thermal threshold table 106. interrupt mask 0 name bit # r/w reset default description
analog integrated circuit device data ? freescale semiconductor 124 mc34708 functional block description therm120 12 rw1c resetb 0x0 120 c thermal threshold therm125 13 rw1c resetb 0x0 125 c thermal threshold therm130 14 rw1c resetb 0x0 130 c thermal threshold clki 15 rw1c resetb 0x0 clock source change scpi 16 rw1c resetb 0x0 short-circuit protection trip detection gpiolv1i 17 rw1c resetb 0x0 gpiolv1 interrupt gpiolv2i 18 rw1c resetb 0x0 gpiolv2 interrupt gpiolv3i 19 rw1c resetb 0x0 gpiolv3 interrupt gpiolv4i 20 rw1c resetb 0x0 gpiolv4 interrupt unused 21 r 0x0 not available reserved 22 r none 0x0 reserved unused 23 r resetb 0x0 not available table 109. register 4, interrupt mask 1 name bit # r/w reset default description 1hzm 0 r/w rtcporb 0x1 1hzi mask bit todam 1 r/w rtcporb 0x1 todai mask bit unused 2 r 0x1 not available pwron1m 3 r/w offb 0x1 pwron1 mask bit pwron2m 4 r/w offb 0x1 pwron2 mask bit wdiresetm 5 r/w rtcporb 0x1 wdireseti mask bit sysrstm 6 r/w rtcporb 0x1 sysrsti mask bit rtcrstm 7 r/w rtcporb 0x1 rtcrsti mask bit pcm 8 r/w offb 0x1 pci mask bit warmm 9 r/w rtcporb 0x1 warmi mask bit memhldm 10 r/w rtcporb 0x1 memhldi mask bit therm110m 11 r/w resetb 0x1 therm110 mask bit therm120m 12 r/w resetb 0x1 therm120 mask bit therm125m 13 r/w resetb 0x1 therm125 mask bit therm130m 14 r/w resetb 0x1 therm130 mask bit clkm 15 r/w resetb 0x1 clki mask bit scpm 16 r/w resetb 0x1 short-circuit protection trip mask bit gpiolv1m 17 r/w resetb 0x1 gpiolv1 interrupt mask bit gpiolv2m 18 r/w resetb 0x1 gpiolv2 interrupt mask bit gpiolv3m 19 r/w resetb 0x1 gpiolv3 interrupt mask bit gpiolv4m 20 r/w resetb 0x1 gpiolv4 interrupt mask bit unused 21 r 0x0 not available table 108. register 3, interrupt status 1 name bit # r/w reset default description
analog integrated circuit device data ? 125 freescale semiconductor mc34708 functional bloc k description reserved 22 r none 0x0 reserved unused 23 r 0x1 not available table 110. register 5, interrupt sense 1 name bit # r/w reset default description unused 2-0 r 0x0 not available pwron1s 3 r none s pwron1i sense bit pwron2s 4 r none s pwron2i sense bit unused 10-5 r 0x0 not available therm110s 11 r none s therm110 sense bit therm120s 12 r none s therm120 sense bit therm125s 13 r none s therm125 sense bit therm130s 14 r none s therm130 sense bit clks 15 r none 0x0 clki sense bit unused 21-16 r 0x00 not available reserved 22 r none 0x0 reserved unused 23 r none 0x0 not available table 111. register 6, power up mode sense name bit # r/w reset default (73) description ictests 0 r none s ictest sense state pums1s 1 r none l pums1 state pums2s 2 r none l pums2 state pums3s 3 r none l pums3 state pums4s 4 r none l pums4 state pums5s 5 r none l pums5 state unused 8-6 r 0x0 not available reserved 9 r none 0x0 reserved unused 23-10 r 0x0000 not available 73. l = loaded pumsx level at startup. table 112. register 7, identification name bit # r/w reset default description metal_layer_rev[2:0] 2-0 r none x metal layer version pass 2.4 =100 full_layer_rev[2:0] 5-3 r none x full layer version pass 2.4 = 010 fin[2:0] 8-6 r none x fin version pass 2.4 = 000 table 109. register 4, interrupt mask 1 name bit # r/w reset default description
analog integrated circuit device data ? freescale semiconductor 126 mc34708 functional block description fab[2:0] 11-9 r none x fab version pass 2.4 = 000 unused 18-12 r 0x0 not available page[4:0] 23-19 r/w digresetb 0x0 spi page table 113. register 8, regulator fault sense name bit # r/w reset default description sw1fault 0 r none s sw1 fault detection reserved 1 r none 0x0 reserved sw2fault 2 r none s sw2 fault detection sw3fault 3 r none s sw3 fault detection sw4afault 4 r none s sw4a fault detection sw4bfault 5 r none s sw4b fault detection sw5fault 6 r none s sw5 fault detection swbstfault 7 r none s swbst fault detection vusbfault 8 r none s vusb fault detection vusb2fault 9 r none s vusb2 fault detection vdacfault 10 r none s vdac fault detection vgen1fault 11 r none s vgen1 fault detection vgen2fault 12 r none s vgen2 fault detection unused 22-13 r 0x00 not available regscpen 23 r/w resetb 0x0 regulator short-ci rcuit protect enable table 114. register 9 , reserved name bit # r/w reset default description reserved 1-23 r none 0x000020 reserved table 115. register 10, reserved name bit # r/w reset default description reserved 1-23 r none 0x00013a reserved table 116. register 11, reserved name bit # r/w reset default description reserved 1-23 r none 0x000000 reserved table 117. register 12, unused name bit # r/w reset default description unused 23-0 r 0x000000 not available table 112. register 7, identification name bit # r/w reset default description
analog integrated circuit device data ? 127 freescale semiconductor mc34708 functional bloc k description table 118. register 13, power control 0 name bit # r/w reset default description pcen 0 r/w rtcporb 0x0 power cut enable pccounten 1 r/w rtcporb 0x0 power cut counter enable warmen 2 r/w rtcporb 0x0 warm start enable useroffspi 3 r/w resetb 0x0 spi command for entering user off modes drm 4 r/w rtcporb (74) 0x0 keeps vsrtc and clk32kmcu on for all states useroffclk 5 r/w rtcporb 0x0 keeps the clk32kmcu active during user off clk32kmcuen 6 r/w rtcporb 0x1 enables the clk32kmcu unused 8-7 r 0x00 not available pcutexpb 9 r/w rtcporb 0x0 pcutexpb=1 at a startup event indicates that pcut timer did not expire (assuming it was set to 1 after booting) unused 18-10 r 0x000 not available reserved 19 r none 0x0 reserved vcoin[2:0] 22-20 r/w rtcporb 0x00 coin cell charger voltage setting coinchen 23 r/w rtcporb 0x0 coin cell charger enable notes: 74. reset by rtcporb but not during a glbrst (global reset) table 119. register 14, power control 1 name bit # r/w reset default description pct[7:0] 7-0 r/w rtcporb 0x00 power cut timer pccount[3:0] 11-8 r/w rtcporb 0x00 power cut counter pcmaxcnt[3:0] 15-12 r/w rtcporb 0x00 maximum allowed number of power cuts unused 23-16 r 0x00 not available table 120. register 15, power control 2 name bit # r/w reset default description restarten 0 r/w rtcporb 0x0 enables automatic restart after a system reset pwron1rsten 1 r/w rtcporb 0x0 enables system reset on pwron1 pin pwron2rsten 2 r/w rtcporb 0x0 enables system reset on pwron2 pin unused 3 r 0x0 not available pwron1dbnc[1:0] 5-4 r/w rtcporb 0x00 sets debounce time on pwron1 pin pwron2dbnc[1:0] 7-6 r/w rtcporb 0x00 sets debounce time on pwron2 pin glbrsttmr[1:0] 9-8 r/w rtcporb 0x01 sets global reset time standbyinv 10 r/w rtcporb 0x0 if set then standby is interpreted as active low unused 11 r 0x0 not available wdireset 12 r/w resetb 0x0 enables system reset through wdi spidrv[1:0] 14-13 r/w rtcporb 0x01 spi drive strength unused 16-15 r 0x00 not available
analog integrated circuit device data ? freescale semiconductor 128 mc34708 functional block description clk32kdrv[1:0] 18-17 r/w rtcporb 0x01 clk32k and clk32kmcu drive strength (master control bits) unused 20-19 r 0x00 not available on_stby_lp 21 r/w resetb 0x0 on standby low power mode 0 = low power mode disabled 1 =low power mode enabled stbydly[1:0] 23-22 r/w resetb 0x01 standby delay control table 121. register 16, memory a name bit # r/w reset default description mema[23:0] 23-0 r/w rtcporb 0x000000 backup memory a table 122. register 17, memory b name bit # r/w reset default description memb[23:0] 23:0 r/w rtcporb 0x000000 backup memory b table 123. register 18, memory c name bit # r/w reset default description memc[23:0] 23-0 r/w rtcporb 0x000000 backup memory c table 124. register 19, memory d name bit # r/w reset default description memd[23:0] 23-0 r/w rtcporb 0x000000 backup memory d table 125. register 20, rtc time name bit # r/w reset default description tod[16:0] 16-0 r/w rtcporb (75) 0x00000 time of day counter rtccal[4:0] 21-17 r/w rtcporb (75) 0x00 rtc calibration count rtccalmode[1:0] 23-22 r/w rtcporb (75) 0x0 rtc calibration mode notes 75. reset by rtcporb but not during a glbrst (global reset) table 126. register 21, rtc alarm name bit # r/w reset default description toda[16:0] 16-0 r/w rtcporb (76) 0x1ffff time of day alarm unused 22-17 r 0x00 not available rtcdis 23 r/w rtcporb (76) 0x0 disable rtc notes 76. reset by rtcporb but not during a glbrst (global reset) table 120. register 15, power control 2 name bit # r/w reset default description
analog integrated circuit device data ? 129 freescale semiconductor mc34708 functional bloc k description table 127. register 22, rtc day name bit # r/w reset default description day[14:0] 14-0 r/w rtcporb (77) 0x0000 day counter unused 23-15 r 0x000 not available notes 77. reset by rtcporb but not during a glbrst (global reset) table 128. register 23, rtc day alarm name bit # r/w reset default description daya[14:0] 14-0 r/w rtcporb (78) 0x7fff day alarm unused 23-15 r 0x000 not available notes 78. reset by rtcporb but not during a glbrst (global reset) table 129. register 24, regulator 1a/b voltage name bit # r/w reset default description sw1a[5:0] 5-0 r/wm none * sw1 setting in normal mode sw1astby[5:0] 11-6 r/wm none * sw1 setting in standby mode reserved 23-12 r none * not available table 130. register 25, regulator 2 & 3 voltage name bit # r/w reset default description sw2[5:0] 5-0 r/wm none * sw2 setting in normal mode sw2stby[5:0] 11-6 r/wm none * sw2 setting in standby mode sw3[4:0] 16-12 r/wm none * sw3 setting in normal mode unused 17 r 0x0 not available sw3stby[4:0] 22-18 r/wm none * sw3 setting in standby mode unused 23 r 0x0 not available table 131. register 26, regulator 4a/b name bit # r/w reset default description sw4a[0:4] 4-0 r/wm none * sw4a setting in normal mode sw4astby[4:0] 9-5 r/wm none * sw4a setting in standby mode sw4ahi[1:0] 11-10 r/wm none * sw4a high setting sw4b[4:0] 16-12 r/wm none * sw4b setting in normal mode sw4bstby[4:0] 21-17 r/wm resetb * sw4b setting in standby mode sw4bhi[1:0] 23-22 r/wm resetb * sw4b high setting
analog integrated circuit device data ? freescale semiconductor 130 mc34708 functional block description table 132. register 27, regulator 5 voltage name bit # r/w reset default description sw5[4:0] 4-0 r/wm none * sw4 setting in normal mode unused 9-5 r * not available sw5stby[4:0] 14-10 r/wm none * sw5 setting in standby mode unused 23-15 r 0x000 not available table 133. register 28, regulators 1 & 2 operating mode name bit # r/w reset default description sw1amode[3:0] 3-0 r/w resetb 0xa sw1a operating mode sw1amhmode 4 r/w offb 0x0 sw1a memory hold mode sw1auomode 5 r/w offb 0x0 sw1a user off mode sw1dvsspeed[1:0] 7-6 r/w resetb 0x1 sw1 dvs1 speed unused 13-8 r 0x00 not available sw2mode[3:0] (79) 17-14 r/w resetb 0xa sw2 operating mode sw2mhmode 18 r/w offb 0x0 sw2 memory hold mode sw2uomode 19 r/w offb 0x0 sw2 user off mode sw2dvsspeed[1:0] 21-20 r/w resetb 0x01 sw2 dvs1 speed pllen 22 r/w resetb 0x1 pll enable pllx 23 r/w resetb 0x0 pll multiplication factor notes 79. swxmode[3:0] bits will be reset to their default values by the startup sequencer, based on pums settings. an enabled switch will default to aps mode for both normal and standby operation. table 134. register 29, regulators 3, 4, and 5 operating mode name bit # r/w reset default description sw3mode[3:0] 3-0 r/w resetb 0xa sw3 operating mode sw3mhmode 4 r/w offb 0x0 sw3 memory hold mode sw3uomode 5 r/w offb 0x0 sw3 user off mode sw4amode[3:0] 9-6 r/w resetb 0xa sw4a operating mode sw4amhmode 10 r/w offb 0x0 sw4a memory hold mode sw4auomode 11 r/w offb 0x0 sw4a user off mode sw4bmode[3:0] 15-12 r/w resetb 0xa sw4b operating mode sw4bmhmode 16 r/w offb 0x0 sw4b memory hold mode sw4buomode 17 r/w offb 0x0 sw4b user off mode sw5mode[3:0] (80) 21-18 r/w resetb 0xa sw5 operating mode sw5mhmode 22 r/w offb 0x0 sw5 memory hold mode sw5uomode 23 r/w offb 0x0 sw5 user off mode notes 80. swxmode[3:0] bits will be reset to their default values by the startup sequencer, based on pums settings. an enabled regulator will default to aps mode for both normal and standby operation.
analog integrated circuit device data ? 131 freescale semiconductor mc34708 functional bloc k description table 135. register 30, regulator setting 0 name bit # r/w reset default description vgen1[2:0] 2-0 r/wm resetb * vgen1 setting unused 3 r 0x0 not available vdac[1:0] 5-4 r/wm resetb * vdac setting vgen2[2:0] 8-6 r/wm resetb * vgen2 setting vpll[1:0] 10-9 r/wm resetb * vpll setting vusb2[1:0] 12-11 r/wm resetb * vusb2 setting unused 23-13 r 0x000 not available table 136. register 31 , swbst control name bit # r/w reset default description swbst[1:0] 1-0 r/w none * swbst setting swbstmode[1:0] 3-2 r/w resetb 0x2 swbst mode spare 4 r/w resetb 0x0 not available swbststbymode[1:0] 6-5 r/w resetb 0x2 swbst standby mode spare 7 r/w resetb 0x0 not available unused 23-8 r 0x0000 not available table 137. register 32, regulator mode 0 name bit # r/w reset default description vgen1en 0 r/w none * vgen1 enable vgen1stby 1 r/w resetb 0x0 vgen1 controlled by standby vusbsel 2 r/w none * slave or host configuration for vbus vusben 3 r/w resetb 0x1 vusb enable (pums4:1=[0100]). also reset to 1 by invalid vbus vdacen 4 r/w none * vdac enable vdacstby 5 r/w resetb 0x0 vdac controlled by standby vdacmode 6 r/w resetb 0x0 vdac operating mode unused 9-7 r 0x0 not available vrefddren 10 r/w none * vrefddr enable vgen2config 11 r/w none * pums5 tied to ground = 0: vgen2 with external pnp pums5 tied to vcroredig =1:vgen2 internal pmos vgen2en 12 r/w none * vgen2 enable vgen2stby 13 r/w resetb 0x0 vgen2 controlled by standby vgen2mode 14 r/w resetb 0x0 vgen2 operating mode vpllen 15 r/w none * vpll enable vpllstby 16 r/w resetb 0x0 vpll controlled by standby vusb2config 17 r/w none * pums5 tied to ground = 0: vusb2 with external pnp pums5 tied to vcroredig =1:vusb2 internal pmos vusb2en 18 r/w none * vusb2 enable
analog integrated circuit device data ? freescale semiconductor 132 mc34708 functional block description vusb2stby 19 r/w resetb 0x0 vusb2 controlled by standby vusb2mode 20 r/w resetb 0x0 vusb2 operating mode unused 23-21 r 0x0 not available table 138. register 33, gpiolv0 control name bit # r/w reset default description dir 0 r/w resetb 0x0 gpiolv0 direction 0: input 1: output din 1 r/w resetb 0x0 input state of gpiolv0 pin 0: input low 1: input high dout 2 r/w resetb 0x0 output state of gpiolv0 pin 0: output low 1: output high hys 3 r/w resetb 0x1 hysteresis 0: cmos in 1: hysteresis dbnc[1:0] 5-4 r/w resetb 0x0 gpiolv0 input debounce time 00: no debounce 01: 10 ms debounce 10: 20 ms debounce 11: 30 ms debounce int[1:0] 7-6 r/w resetb 0x0 gpiolv0 interrupt control 00: none 01: falling edge 10: rising edge 11: both edges pke 8 r/w resetb 0x0 pad keep enable 0: off 1: on ode 9 r/w resetb 0x0 open drain enable 0: cmos 1: od dse 10 r/w resetb 0x0 drive strength enable 0: 4.0 ma 1: 8.0 ma pue 11 r/w resetb 0x1 pull-up/down enable 0: pull-up/down off 1: pull-up/down on (default) pus[1:0] 13-12 r/w resetb 0x3 pull-up/pull-down select 00: 10 k pull-down 01: 100 k pull-down 10: 10 k pull-up 11: 100 k pull-up table 137. register 32, regulator mode 0 name bit # r/w reset default description
analog integrated circuit device data ? 133 freescale semiconductor mc34708 functional bloc k description sre[1:0] 15-14 r/w resetb 0x0 slew rate enable 00: slow (default) 01: normal 10: fast 11: very fast unused 23-16 r 0x00 not available table 139. register 34, gpiolv1 control name bit # r/w reset default description dir 0 r/w resetb 0x0 gpiolv1directon 0: input 1: output din 1 r/w resetb 0x0 input state of gpiolv1 pin 0: input low 1: input high dout 2 r/w resetb 0x0 output state of gpiolv1 pin 0: output low 1: output high hys 3 r/w resetb 0x1 hysteresis 0: cmos in 1: hysteresis dbnc[1:0] 5-4 r/w resetb 0x0 gpiolv1 input debounce time 00: no debounce 01: 10 ms debounce 10: 20 ms debounce 11: 30 ms debounce int[1:0] 7-6 r/w resetb 0x0 gpiolv1 interrupt control 00: none 01: falling edge 10: rising edge 11: both edges pke 8 r/w resetb 0x0 pad keep enable 0: off 1: on ode 9 r/w resetb 0x0 open drain enable 0: cmos 1: od dse 10 r/w resetb 0x0 drive strength enable 0: 4.0 ma 1: 8.0 ma pue 11 r/w resetb 0x1 pull-up/down enable 0: pull-up/down off 1: pull-up/down on (default) pus[1:0] 13:12 r/w resetb 0x3 pull-up/pull-down select 00: 10 k pull-down 01: 100 k pull-down 10: 10 k pull-up 11: 100 k pull-up table 138. register 33, gpiolv0 control name bit # r/w reset default description
analog integrated circuit device data ? freescale semiconductor 134 mc34708 functional block description sre[1:0] 15-14 r/w resetb 0x0 slew rate enable 00: slow (default) 01: normal 10: fast 11: very fast unused 23-16 r 0x00 not available table 140. register 35, gpiolv2 control name bit # r/w reset default description dir 0 r/w resetb 0x0 gpiolv2 direction 0: input 1: output din 1 r/w resetb 0x0 input state of gpiolv2 pin 0: input low 1: input high dout 2 r/w resetb 0x0 output state of gpiolv2 pin 0: output low 1: output high hys 3 r/w resetb 0x1 hysteresis 0: cmos in 1: hysteresis dbnc[1:0] 5-4 r/w resetb 0x0 gpiolv2 input debounce time 00: no debounce 01: 10 ms debounce 10: 20 ms debounce 11: 30 ms debounce int[1:0] 7-6 r/w resetb 0x0 gpiolv2 interrupt control 00: none 01: falling edge 10: rising edge 11: both edges pke 8 r/w resetb 0x0 pad keep enable 0: off 1: on ode 9 r/w resetb 0x0 open drain enable 0: cmos 1: od dse 10 r/w resetb 0x0 drive strength enable 0: 4.0 ma 1: 8.0 ma pue 11 r/w resetb 0x1 pull-up/down enable 0: pull-up/down off 1: pull-up/down on (default) pus[1:0] 13-12 r/w resetb 0x3 pull-up/pull-down select 00: 10 k pull-down 01: 100 k pull-down 10: 10 k pull-up 11: 100 k pull-up table 139. register 34, gpiolv1 control name bit # r/w reset default description
analog integrated circuit device data ? 135 freescale semiconductor mc34708 functional bloc k description sre[1:0] 15-14 r/w resetb 0x0 slew rate enable 00: slow (default) 01: normal 10: fast 11: very fast unused 23-16 r 0x00 not available table 141. register 36, gpiolv3 control name bit # r/w reset default description dir 0 r/w resetb 0x0 gpiolv3 direction 0: input 1: output din 1 r/w resetb 0x0 input state of gpiolv3 pin 0: input low 1: input high dout 2 r/w resetb 0x0 output state of gpiolv3 pin 0: output low 1: output high hys 3 r/w resetb 0x1 hysteresis 0: cmos in 1: hysteresis dbnc[1:0] 5-4 r/w resetb 0x0 gpiolv3 input debounce time 00: no debounce 01: 10 ms debounce 10: 20 ms debounce 11: 30 ms debounce int[1:0] 7-6 r/w resetb 0x0 gpiolv3 interrupt control 00: none 01: falling edge 10: rising edge 11: both edges pke 8 r/w resetb 0x0 pad keep enable 0: off 1: on ode 9 r/w resetb 0x0 open drain enable 0: cmos 1: od dse 10 r/w resetb 0x0 drive strength enable 0: 4.0 ma 1: 8.0 ma pue 11 r/w resetb 0x1 pull-up/down enable 0: pull-up/down off 1: pull-up/down on (default) pus[1:0] 13-12 r/w resetb 0x3 pull-up/pull-down select 00: 10 k pull-down 01: 100 k pull-down 10: 10 k pull-up 11: 100 k pull-up table 140. register 35, gpiolv2 control name bit # r/w reset default description
analog integrated circuit device data ? freescale semiconductor 136 mc34708 functional block description sre[1:0] 15-14 r/w resetb 0x0 slew rate enable 00: slow (default) 01: normal 10: fast 11: very fast unused 23-16 r 0x00 not available table 142. register 37, usb timing name bit # r/w reset default description device_wake_up[3:0] 3-0 r/w musbrstb 0x0 the periodical sampling time of the id line in the power-save mode and standby mode; the periodical time of adc conversion of the resistance at id pin when raw data = 0. 0000: 50 ms 0001: 100 ms 0010: 150 ms 0011: 200 ms 0100: 300 ms keypress[3:0] 7-4 r/w musbrstb 0x0 normal key press duration 0000: 100 ms 0001: 200 ms 0010: 300 ms ... long_keypress[3:0] 11-8 r/w musbrstb 0x0 long key press duration 0000: 300 ms 0001: 400 ms 0010: 500 ms ... switching_wait 15-12 r/w musbrstb 0x0 waiting time before switching the analog or digital switches: 0000: 10 ms 0001: 30 ms 0010: 50 ms ... td 19-16 r/w musbrstb 0x0 time delay to start the powere d accessory identification flow after detecting the bus voltage 0000: 100 ms 0001: 200 ms 0010: 300 ms 0011: 400 ms 0100: 500 ms ... 1111:1600 ms the time for no activity in the switches before entering the power save mode automatically for audio type 1 or tty device 0000: 1 s 0001: 2 s ... 1001:10s ... 1111:16 s table 141. register 36, gpiolv3 control name bit # r/w reset default description
analog integrated circuit device data ? 137 freescale semiconductor mc34708 functional bloc k description unused 22-20 r 0x0 not available readvalid 23 r musbrstb 0x0 read data valid 0: data not valid 1: data valid table 143. register 38, usb button name bit # r/w reset default description send_end 0 r/c musbrstb 0x0 1: the send_end button is pressed s1 1 r/c musbrstb 0x0 1: button 1 is pressed s2 2 r/c musbrstb 0x0 1: button 2 is pressed s3 3 r/c musbrstb 0x0 1: button 3 is pressed s4 4 r/c musbrstb 0x0 1: button 4 is pressed s5 5 r/c musbrstb 0x0 1: button 5 is pressed s6 6 r/c musbrstb 0x0 1: button 6 is pressed s7 7 r/c musbrstb 0x0 1: button 7 is pressed s8 8 r/c musbrstb 0x0 1: button 8 is pressed s9 9 r/c musbrstb 0x0 1: button 9 is pressed s10 10 r/c musbrstb 0x0 1: button 10 is pressed s11 11 r/c musbrstb 0x0 1: button 11 is pressed s12 12 r/c musbrstb 0x0 1: button 12 is pressed error 13 r/c musbrstb 0x0 1: button error occurred unknown 14 r/c musbrstb 0x0 1: an unknown button is pressed unused 23-15 r 0x000 not available table 144. register 39, usb control name bit # r/w reset default description wait 0 r/w musbrstb 0x1 wait or not to wait for the command from the baseband before turning on the analog or digital switches for attached accessory 0: wait until this bit is changed to 1. turn on the switches immediately when this bit is changed to 1. 1: wait for only the time programmed by the switching wait bits in timing set 2 register before turning on the switches. manual s/w 1 r/w musbrstb 0x1 manual or automatic switching of the switches 0: manual: the switches are c ontrolled by the manual s/w registers. 1: auto: the switches are controlled by the device type registers rawdata 2 r/w musbrstb 0x1 interrupt behavior selection 0: enable the adc conversion periodically and report the adc result changes on id pin to the host. 1: enable the key press monitor circuit to detect the id pin status changes and report the key press events to the host. table 142. register 37, usb timing name bit # r/w reset default description
analog integrated circuit device data ? freescale semiconductor 138 mc34708 functional block description switch_open 3 r/w musbrstb 0x1 switch connection selection 0: open all switches 1: switch selection according to the manual s/w bit. reset 4 rwm musbrstb 0x0 soft reset. when written to 1, the ic is reset. once the reset is complete, the rst bit is set and the reset bit is cleared automatically. 1: to soft-reset the ic tty_spkl 5 r/w musbrstb 0x0 spk_l to dm switch control 0: turn off the spk_l to dm switch 1: turn on the spk_l to dm switch for tty rst 6 r/c musbrstb x this bit indicates if a chip rese t has occurred. this bit will be cleared once being read. 0: no. 1: yes. active 7 r/w musbrstb x indicate either the device is in active mode 0: standby 1: active clk_rst 8 r/c musbrst 0x1 not available votgen 9 r/w resetb 0x0 enables the otg switch and the gotg switch unused 10 r 0x0 not available reserved 11 r none 0x0 reserved swhold 12 r/w musbrstb 0x1 switch hold 0: run state machine and allow detection of accessory 1: holds off state machine until baseband comes up reserved 14-13 r none 0x0 reserved vbus switching[1:0] 16-15 r/w musbrstb 0x0 vbus line switching configuration when manual s/w = 0 00: open all switches motg, m0 01: n/a 10: vbus connects to mic. m0, motg. others: open all switches connected to the vbus line dp switching[2:0] 19-17 r/w musbrstb 0x0 dp line switching configur ation when manual s/w = 0 000: open all switches 001: dp connected to d+, dm connected to d- 010: dp connected to spk_r, dm connected to spk_l 011: dp connected to rxd, dm connected to txd others: open all switches connected to the dp pin and dm pin dm switching[2:0] 22-20 r/w musbrstb 0x0 dm line switching configur ation when manual s/w = 0 000: open all switches 001: dp connected to d+, dm connected to d- 010: dp connected to spk_r, dm connected to spk_l 011: dp connected to rxd, dm connected to txd others: open all switches connected to the dp pin and dm pin readvalid 23 r musbrstb 0x0 read data valid 0: data not valid 1: data valid table 144. register 39, usb control name bit # r/w reset default description
analog integrated circuit device data ? 139 freescale semiconductor mc34708 functional bloc k description table 145. register 40, usb device type name bit # r/w reset default description audio type 1 0 r musbrstb 0x0 1: an audio type 1 accessory is attached audio type 2 1 r musbrstb 0x0 1: an audio type 2 accessory is attached usb 2 r musbrstb 0x0 1: a usb host is attached uart 3 r musbrstb 0x0 1: a uart cable is attached 5w chg 4 r musbrstb 0x0 1: a 5-wire charger (type 1 or 2) is attached usb chg 5 r musbrstb 0x0 1: a usb charger is attached dedicated chg 6 r musbrstb 0x0 1: a dedicated charger is attached usb otg 7 r musbrstb 0x0 1: a usb otg accessory is attached ppd 8 r musbrstb 0x0 1: a phone powered device is attached tty 9 r musbrstb 0x0 1: a tty converter is attached a/v 10 r musbrstb 0x0 1: an audio/video cable is attached avchrg 11 r musbrstb 0x0 1: an audio/video charger is attached usbjig1 12 r musbrstb 0x0 1: a usb jig cable 1 is attached usbjig2 13 r musbrstb 0x0 1: a usb jig cable 2is attached uartjig1 14 r musbrstb 0x0 1: a uart jig cable 1is attached uartjig2 15 r musbrstb 0x0 1: a uart jig cable 2 is attached id_factory 16 r musbrstb 0x0 1: a factory cable is attached unk_device 17 r musbrstb 0x0 1: device not recognized unused 18 r 0x0 not available adcidresult[4:0] 23-19 r musbrstb 0x00 adc result value of the resistance at id pin table 146. register 41 and 42, unused name bit # r/w reset default description unused 0-23 r 0x000000 not available table 147. register 43, adc 0 name bit # r/w reset default description aden 0 r/w digresetb 0x0 enables adc from the low power mode adstart 1 r/w digresetb 0x0 request a start of the adc reading sequencer adcont 2 r/w digresetb 0x0 run adc reads continuously when high or one time when low. note that the tsstart request will have higher priority adhold 3 r/w digresetb 0x0 hold the adc reading sequencer while saved adc results are read from spi adstop[2:0] 6-4 r/w digresetb 0x0 channel selection to stop when complete. always start at 000 and read up to and including this channel value. spare 7 r/w digresetb 0x0 not available therm 8 r/w digresetb 0x0 0 = disable manual led control. 1= enable manual led control spare 11-9 r/w digresetb 0x0 not available
analog integrated circuit device data ? freescale semiconductor 140 mc34708 functional block description tsen 12 r/w digresetb 0x0 enable the touch screen from low power mode. tsstart 13 r/w digresetb 0x0 request a start of the adc reading sequencer for touch screen readings. tscont 14 r/w digresetb 0x0 run adc reads of touch screen continuously when high or one time when low. tshold 15 r/w digresetb 0x0 hold the adc reading sequencer while saved touch screen results are read from spi tsstop[2:0] 18-16 r/w digresetb 0x0 just like the adstop above, but for the touchscreen read programming. this will allow independent code for adc sequence readings and t ouchscreen adc sequence readings. spare 19 r/w digresetb 0x0 not available tspendeten 20 r/w digresetb 0x0 enable the touchscreen pen detection. note that tsen must be off for pen detection. spare 23-21 r/w digresetb 0x0 not available table 148. register 44, adc 1 name bit # r/w reset default description addly1[3:0] 3-0 r/w digresetb 0x0 this will allow delay before the adc readings. addly2[3:0] 7:4 r/w digresetb 0x0 this will allow del ay between each of adc readings in a set. addly3[3:0] 11-8 r/w digresetb 0x0 this will allow delay after the set of adc readings. this delay is only valid between subsequent wrap around reading sequences with adcont tsdly1[3:0] 15-12 r/w digresetb 0x0 this will allow delay before the adc touch screen readings. this is like the addly1, but allows independent programming of touchscreen readings from general purpose adc readings to prevent code replacement in the system. tsdly2[3:0] 19-16 r/w digresetb 0x0 this will allow delay between each of adc touch screen readings in a set. this is li ke the addly2, but allows independent programming of t ouchscreen readings from general purpose adc readings to prevent code replacement in the system. tsdly3[3:0] 23-20 r/w digresetb 0x0 this will allow delay after the set of adc touch screen readings. this delay is only valid between subsequent wrap around reading sequences with ts cont mode. this is like the addly3, but allows independent programming of touchscreen readings from general purpose adc readings to prevent code replacement in the system. table 149. register 45, adc 2 name bit # r/w reset default description adsel0[3:0] 3-0 r/w digresetb 0x0 channel selection to place in adresult0 adsel1[3:0] 7-4 r/w digresetb 0x0 channel selection to place in adresult1 adsel2[3:0] 11-8 r/w digresetb 0x0 channel selection to place in adresult2 adsel3[3:0] 15-12 r/w digresetb 0x0 channel selection to place in adresult3 table 147. register 43, adc 0 name bit # r/w reset default description
analog integrated circuit device data ? 141 freescale semiconductor mc34708 functional bloc k description adsel4[3:0] 19-16 r/w digresetb 0x0 channel selection to place in adresult4 adsel5[3:0] 23-20 r/w digresetb 0x0 channel selection to place in adresult5 table 150. register 46, adc 3 name bit # r/w reset default description adsel6[3:0] 3-0 r/w digresetb 0x0 channel selection to place in adresult6 adsel7[3:0] 7-4 r/w digresetb 0x0 channel selection to place in adresult7 tssel0[1:0] 9-8 r/w digresetb 0x0 touchscreen selection to place in adresult0. select the action for the touchscreen; 00 = dummy to discharge tsref capacitance, 01 = to read x-plate, 10 = to read y-plate, and 11 = to read contact. tssel1[1:0] 11-10 r/w digresetb 0x0 touchscreen selection to place in adresult1. see tssel0 for modes. tssel2[1:0] 13-12 r/w digresetb 0x0 touchscreen selection to place in adresult2. see tssel0 for modes. tssel3[1:0] 15-14 r/w digresetb 0x0 touchscreen selection to place in adresult3. see tssel0 for modes. tssel4[1:0] 17-16 r/w digresetb 0x0 touchscreen selection to place in adresult4. see tssel0 for modes. tssel5[1:0] 19-18 r/w digresetb 0x0 touchscreen selection to place in adresult5. see tssel0 for modes. tssel6[1:0] 21-20 r/w digresetb 0x0 touchscreen selection to place in adresult6. see tssel0 for modes. tssel7[1:0] 23-22 r/w digresetb 0x0 touchscreen selection to place in adresult7. see tssel0 for modes. table 151. register 47, adc 4 name bit # r/w reset default description unused 1-0 r 0x0 not available adresult0[9:0] 11-2 r digresetb 0x000 adc result for adsel0 unused 13-12 r 0x0 not available adresult1[9:0] 23-14 r digresetb 0x000 adc result for adsel1 table 152. register 48, adc5 name bit # r/w reset default description unused 1-0 r 0x0 not available adresult2[9:0] 11-2 r digresetb 0x000 adc result for adsel2 unused 13-12 r 0x0 not available adresult3[9:0] 23-14 r digresetb 0x000 adc result for adsel3 table 149. register 45, adc 2 name bit # r/w reset default description
analog integrated circuit device data ? freescale semiconductor 142 mc34708 functional block description table 153. register 49, adc6 name bit # r/w reset default description unused 1-0 r 0x0 not available adresult4[9:0] 11-2 r digresetb 0x000 adc result for adsel4 unused 13-12 r 0x0 not available adresult5[9:0} 23-14 r digresetb 0x000 adc result for adsel5 table 154. register 50, adc7 name bit # r/w reset default description unused 1:0 r 0x0 not available adresult6[9:0] 11-2 r digresetb 0x000 adc result for adsel6 unused 13-12 r 0x0 not available adresult7[9:0] 23-14 r digresetb 0x000 adc result for adsel7 table 155. register 51, input monitoring name bit # r/w reset default description vbat_trkl[1:0] 1-0 r/w rtcporb 0x0 trickle1 to trickle2 change over threshold 00: 2.8 v 01: 2.9 v 10: 3.0 v 11: 3.1 v reserved 2 r none 0x0 reserved chren 3 r/w rtcporb 0x1 charger enable lowbatt[1:0] 5-4 r/w rtcporb 0x3 turn on detection threshold and low battery warning threshold reserved 23-6 r/w none 0x00000 reserved table 156. register 52, input debounce name bit # r/w reset default description reserved 1-0 r/w none 0x0 reserved vbattdb[1:0] 3-2 r/w resetb 0x3 battery voltage debounce vbusdb[1:0] 5-4 r/w resetb 0x03 vbus debounce reserved 9-6 r/w none 0x0 reserved chrgledovrd 10 r/w resetb 0x0 led override reserved 13-11 r/w none 0x0 reserved sup_ovp_db[1:0] 15-14 r/w resetb 0x3 vbus over voltage debounce die_temp_db[1:0] 17-16 r/w resetb 0x3 die temp comparator debounce reserved 23-18 r none 0x00 reserved
analog integrated circuit device data ? 143 freescale semiconductor mc34708 functional bloc k description table 157. register 53, vbus monitoring name bit # r/w reset default description vbustl[2:0] 2-0 r/w resetb 0x3 vbus threshold low vbusth[2:0] 5-3 r/w resetb 0x3 vbus threshold high reserved 23-6 r/w none 0x00000 reserved table 158. register 54, led control name bit # r/w reset default description chrgledrper[1:0] 1-0 r/w resetb 0x0 charger led red repetition period chrgledrramp 2 r/w resetb 0x0 charger led red channel driver ramp enable chrgledrdc[5:0] 8-3 r/w resetb 0x00 charger led red channel driver duty cycle chrgledr[1:0] 10-9 r/w resetb 0x3 charger led red driver current setting chrgledren 11 r/w resetb 0x0 charger led red enable chrgledgper[1:0] 13-12 r/w resetb 0x0 charger led green repetition period chrgledgramp 14 r/w resetb 0x0 charger led green channel driver ramp enable chrgledgdc[5:0] 20-15 r/w resetb 0x00 charger led green channel driver duty cycle chrgledg[1:0] 22-21 r/w resetb 0x3 charger led green driver current setting chrgledgen 23 r/w resetb 0x0 charger led green enable table 159. register 55, pwm control name bit # r/w reset default description pwm1duty[5:0] 5-0 r/w resetb 0x00 pwm1 duty cycle pwmclkdiv[5:0] 11-6 r/w resetb 0x00 pwm1 clock divide setting pwm2duty[5-0] 17-12 r/w resetb 0x00 pwm2 duty cycle pwm2clkdiv[5:0] 23-18 r/w resetb 0x00 pwm2 clock divide setting table 160. register 56 to 63, unused name bit # r/w reset default description unused 0-23 r 0x000000 not available
analog integrated circuit device data ? freescale semiconductor 144 mc34708 typical applications 8 typical applications the following diagram gives a typical application diagram of the mc34708 pmic together with its functional components. for details on component references and additional component s such as filters, refer to the individual sections. 8.1 application diagram figure 38. typical application schematic bp resetb resetbmcu wdi switchers gndadc adin11 mux 10 bit gp adc int clk32k xtal1 xtal2 gndrtc licell gpio control gpiolv1 gpiolv2 rtc + calibration gndsw2 sw2fb sw2lx sw1in sw2in o/p drive ` gndsw1a sw1fb sw3in o/p drive gndsw3 sw3fb sw3lx gndswbst swbstfb swbstin swbstlx o/p drive pwron1 pums1 monitor timer o/p drive pll 32 khz crystal osc standby gpiolv3 to interrupt section die temp & thermal warning detection lcell switch enables & control spi result registers interrupt inputs gndctrl core control logic, timers, & interrupts 32 khz internal osc gpiolv4 chrgledr input/battery monitoring licell, uid, die temp, gpo4 adin10 clk32kmcu gndreg1 gndreg2 adin9 a/d result a/d control ictest 32 khz buffers output pin input pin bi-directional pin package pin legend spi interface + muxed i2c optional interface cs clk gndspi miso spi registers mosi shift register shift register spivcc to enables & control to trimmed circuits spi control logic trim-in-package startup sequencer decode trim? pumsx control logic li cell charger sw2 lp 1000 ma buck sw3 int mem 500 ma buck swbst 380 ma boost voltage / current sensing & translation mc34708 sw4 dual phase ddr 1000 ma buck vsrtc vsrtc vinrefddr vpll vpll 50 ma pass fet vrefddr 10ma vrefddr spi control vbus vinusb vusb uid connector interface best of supply licell bp reference generation vcoredig gndcore vcore vcoreref v b u s / i d d e t e c t o r s , h o s t a u t o d e t e c t i o n u a r t s w i t c h e s a u d i o s w i t c h e s vusb regulator subsana1 subspwr1 subsref subsgnd subspwr2 subsana3 subsana2 subsldo vinpll pums2 pwron2 glbrst sw5in o/p drive gndsw5 sw5fb sw5lx sw5 i/o 1000 ma buck vusb2 350ma vdacdrv vdac vusb2 vusb2drv vdac 250ma gndachrg sw1alx dvs control cfp cfn battisnsccn chrgledg dm dp dplus dminus ovp spkr sw1pwgd sw2pwgd pwm outputs pwm1 pwm2 spkl mic rxd txd gndsw1b o/p drive sw1blx sw4ain gndsw4a sw4fba o/p drive sw4alx sw4bin gndsw4b sw4bfb o/p drive sw4blx gndusb sw4cfg ledvdd vddlp vgen1 250ma vgen2drv vgen2 vgen2 250ma pass fet vgen1 pass fet vingen1 pums3 pums4 sdwnb digital core pretmr tricklesel chrgfb battisnsn battisnsp bp chrglx vbusvin auxvin gaux gbat bpsns gotg vaux general purpose led drivers sw1 dual phase gp 2000 ma buck sw1cfg valways sw1vsssns vhalf bptherm ntcref batt battisnsccp itric pums5 gpiovdd gndgpio gndref1 gndref2 gndref ldovdd pass fet 100n coin cell battery 2.2u swbst 100pf 1u 1u spi sw5 general purpose adc inputs: i.e., pa thermistor, light sensor, etc. to/from audio ic to/from ap to/from usb cable 100n bp 10u 10u bp bp 22u swbst output (boost) 2.2u 2.2u bp sw4b 1u bp 2.2u 1.0u 2 x22u sw1 output bp 4.7u bp 4.7u 1.0u 22u sw2 output to ap bp 4.7u 1.0u 10u sw3 output 1.0u 10u sw4a output bp 4.7u 4.7u 1.0u 10u sw4b output 1.0u 22u sw5 output bp 4.7u to ap 2.2u bp 2.2u bp sw5 2.2u bp 2.2u vcoredig bp 100n bp to ap to peripherals to gnd, or vcoredig to/from ap on/off button wakeup from ap reset button 32.768 khz crystal 15p sw5 or sw3 gndchrg 0.1uf 100k 100k 100k 100k 100k 1u adin14/tsy1 adin15/tsy2 adin13/tsx2 tsref touch screen interface adin12/tsx1 touch screen interface 2.2u 100n c1 c2 d1 d2 c54 c56 c50 c51 c52 c49 c47 c46 c5 l2 c6/c7 r18 c10 l4 c11 r19 c13 l5 c14 c16 l6 c17 c22 c20 l7 c23 l8 l9 c25 d3 c26 c57 c55 c28 c30 c29 q1 q3 c36 c38 q5 c41 c43 c45 r20 r4 c44 18p y1 r3 c19 d8 d10 d11 d12 d13 d14 2.2uf c34 vin ce vout gnd vddlp 100nf 100nf c58 c59 d15 1.5v ldo
analog integrated circuit device data ? 145 freescale semiconductor mc34708 typical applications 8.2 bill of material the following table provides a complete list of the recomm ended components on a full f eatured system using the mc34708 device. critical components su ch as inductors, transistors, and diodes are provided with a recommended part number, but equivalent components may be used. table 161. mc34708 bill of material (81) item quantity component description vendor comments 1 1 mc34708 freescale pmic charger/battery interface 2 1 c1 10 ? f tdk battery filter 3 2 r1 20 mohm battery sense (optional fo r battery current sensing) 4 1 c2 10 ? f bp/ buck charging capacitor 5 1 c67 1 uf vbus 1 uf input cap 6 1 d2 green led green general purpose led indicator 7 1 d1 red led red general purpose led indicator miscellaneous 8 1 c56 1.0 ? f valways 9 1 c43 100 nf vsrtc 10 1 c50 1.0 ? f vcore 11 1 c51 1.0 ? f vcoredig 12 1 c52 100 pf vddlp 13 1 c49 100 nf vcoreref 14 1 c46 100 nf coin cell 15 1 y1 crystal 32.768 khz cc7 oscillator 16 1 c44 18 pf oscillator load capacitor 17 1 c45 18 pf oscillator load capacitor 18 2 r3, r4 100 k resetb, resetbmcu pull-ups 19 1 r20 100 k sdwnb pull-up boost 20 1 l9 2.2 ? h lps3015-222ml coilcraft boost inductor 21 1 d3 diode bas52 infineon boost diode 22 1 c26 2.2 ? f 16 v boost output capacitor 23 1 c25 22 ? f boost input capacitor
analog integrated circuit device data ? freescale semiconductor 146 mc34708 typical applications sw1 24 2 l2, l3 1.0 ? h vls201612et-1r0n tdk buck 1 inductor (i max < 1.6 amps) 1.0 ? h vls252010et-1r0n tdk optional dual phase inductor (i max ? 2.0 amps) 1.0 ? h brl3225t1rom taiyo yuden optional single phase inductor (i max < 1.6 amps) 1.0 uh lps4012-102nl coilcraft optional single phase inductor (i max ? 2.0 amps) 25 2 c6, c7 22 ? f buck 1 output capacitor 26 1 c5 4.7 ? f buck 1 input capacitor 27 1 d8 diode bas3010-03lrh infineon sw1lx diode sw2 28 1 l4 1.0 ? h vls252010et-1r0n tdk buck 2 inductor 29 1 c11 22 ? f buck 2 output capacitor 30 1 c10 4.7 ? f buck 2 input capacitor 31 1 d10 diode bas3010-03lrh infineon sw2lx diode sw3 32 1 l5 1.0 ? h vls201612et-1r0n tdk buck 3 inductor 33 1 c14 10 ? f buck 3 output capacitor 34 1 c13 4.7 ? f buck 3 input capacitor 35 1 d11 diode bas3010-03lrh infineon sw3lx diode sw4a 36 1 l6 1.0 ? h vls201612et-1r0n tdk buck 4a inductor 37 0 1.0 ? h vls252010et-1r0n tdk optional inductor 38 1 c17 10 ? f buck 4a output capacitor 39 1 c16 4.7 ? f buck 4a input capacitor 40 1 d12 diode bas3010-03lrh infineon sw4alx diode sw4b 41 1 l7 1.0 ? h vls201612et-1r0n tdk buck 4b inductor 42 0 - 1.0 ? h vls25010et-1r0n tdk optional inductor 43 1 c20 10 ? f buck 4b output capacitor 44 1 c19 4.0 ? f buck 4b input capacitor 45 1 d13 diode bas3010-03lrh infineon sw4blx diode sw5 46 1 l8 1.0 ? h vls252010et-1r0n tdk buck 5 inductor 47 1 c23 22 ? f buck 5 output capacitor 48 1 c22 4.7 ? f buck 5 input capacitor table 161. mc34708 bill of material (81) item quantity component description vendor comments
analog integrated circuit device data ? 147 freescale semiconductor mc34708 typical applications 49 1 d14 diode bas3010-03lrh infineon sw5lx diode vpll 50 1 c30 2.2 ? f vpll vrefddr 51 1 c57 100 nf vhalf 0.1 uf caps 52 1 c28 1.0 ? f vrefddr vdac 53 1 q3 pnp transistor ? nss12100uw3 ? 2sb1733 on semi rohm vdac pnp 54 1 c36 2.2 ? f vvdac vusb2 55 1 q1 pnp transistor ? nss12100uw3 ? 2sb1733 on semi rohm vusb2 pnp 56 1 c29 2.2 ? f vusb2 vusb 57 1 c47 2.2 ? f vusb vgen1 58 1 c38 4.7 ? f vgen1 vgen2 59 1 q5 pnp transistor ? nss12100uw3 ? 2sb1733 on semi rohm vgen2 pnp 60 1 c41 2.2 ? f vgen2 workarounds 61 1 u2 1.5 v ldo ? ncp4682 ? ncp4685 on semi 1.5 v ldo for workaround. see erratum #23 on er34708 62 1 d15 schottky diode low voltage schottky diode 63 1 c58 100 nf ldo input capacitor 1 c59 100 nf ldo output capacitor notes 81. freescale does not assume liability, endorse, or warrant comp onents from external manufacturers that are referenced in circu it drawings or tables. while freescale offers component recommendations in this c onfiguration, it is the customer?s responsibility to validate their application. table 161. mc34708 bill of material (81) item quantity component description vendor comments
analog integrated circuit device data ? freescale semiconductor 148 mc34708 typical applications 8.3 mc34708 layout guidelines 8.3.1 general board recommendations 1. it is recommended to use an 8 layer board stack-up arranged as follows: ? high current signal ?gnd ?signal ? power ? power ?signal ?gnd ? high current signal 2. allocate top and bottom pcb layers for power routin g (high current signals), copper-pour the unused area. 3. use internal layers sandwiched between two gnd planes for the signal routing. 8.3.2 component placement sense resistors should be placed as close to the ic as possible. route the high cu rrent path flowing from vbatt to battisnsn as thick and as short as possible to reduce power losses. 8.3.3 general routing requirements 1. some recommended things to keep in mind for manufacturability: ? via in pads require a 4.5 mil minimum annular ring. pad must be 9.0 mils larger than the hole ? max copper thickness for lines less than 5.0 mils wide is 0.6 oz copper ? minimum allowed spacing between line and hole pad is 3.5 mils ? minimum allowed spacing between line and line is 3.0 mils 2. care must be taken with swxfb pins traces. these signals are susceptible to noise and must be routed far away from power, clock, or high power signals, like the ones on the swxin, swx, swxlx, swbstin , swbst, and swbstlx pins. 3. shield feedback traces of the switching regulators and keep them as short as possible (trace them on the bottom so the ground and power planes shield these traces). 4. sense pins must be directly connected to the 0.02 ohm sense resistor r1 (battisnsn and battisnsp). 5. avoid coupling trace between important signal/low noise supplies (like vrefcore, vcore, vcoredig) from any switching node (i.e. sw1alxx, sw2lxx, sw 3lxx, sw4alx, sw4blx, sw5lxx and swbstlxx). 6. make sure that all components related to an specific block are referenced to the corresponding ground, e.g. all components related to the sw1 converter must referenced to gndsw1a1 and gndsw1a2. 8.3.4 parallel routing requirements 1. spi/i 2 c signal routing: ? clk is the fastest signal of the system, so it must be given special care. here are some tips for routing the communication signals: ? to avoid contamination of these delicate signals by nearby high power or high frequency signals, it is a good practice to shield them with ground planes placed on adjacent layers . make sure the ground plane is uniform throughout the whole signal trace length.
analog integrated circuit device data ? 149 freescale semiconductor mc34708 typical applications figure 39. recommended shielding for critical signals. ? these signals can be placed on an outer layer of the board to reduce their capacitance in respect to the ground plane. ? the crystal connected to the xtal1 and xtal2 pi ns must not have a ground plane directly below. ? the following are clock signals: clk, clk32k, clk32kmcu, xtal1, and xtal2. these signals must not run parallel to each other, or in the same routing layer. if it is necessary to run clock signals parallel to each other, or parallel to any ot her signal, then follow a max parallel rule as follows: ? up to 1 inch parallel length ? 25 mil minimum separation ? up to 2 inch parallel length ? 50 mil minimum separation ? up to 3 inch parallel length ? 100 mil minimum separation ? up to 4 inch parallel length ? 250 mil minimum separation ? care must be taken with these signals not to contami nate analog signals, as they are high frequency signals. another good practice is to trace them perpendicularly on different laye rs, so there is a minimum area of proximity between signals. 2. the traces battisnsn and battisnsp that go to the r1 resistor must run in parallel. 8.3.5 differential routing 1. dp and dm traces should be routed as 90 ohm differential signals. 2. dplus and dminus traces should be routed as 90 ohm differential signals. 8.3.6 switching regulator layout recommendations 1. per design, the mc34708 is designed to operate with only 1 input bulk capacitor. however, it is recommended to add a high frequency filter input capacitor (cin_h f), to filter out any noise at the regulator input. this capacitor should be in the range of 100 nf and should be placed right next to or under the ic, closest to the ic pins. 2. make high-current ripple traces low inductance (short, high w/l ratio). 3. make high-current traces wide or copper islands. 4. make high-current traces symetrical for dual?phase regulators (sw1, sw4).
analog integrated circuit device data ? freescale semiconductor 150 mc34708 typical applications figure 40. generic buck regulator architecture figure 41. recommended layout for switching regulators. diver controller swxvin swxlx swxfb c out c in l gndswx swx bp compensation c in_hf d
analog integrated circuit device data ? 151 freescale semiconductor mc34708 typical applications 8.4 thermal considerations 8.4.1 rating data the thermal rating data of the packages has been simulated with the results listed in table 5 . junction to ambient thermal resistance nomenclatu re: the jedec spec ification reserves the symbol r ja or ja (theta-ja) strictly for junction-to-ambient thermal resistance on a 1s test board in natural convection environment. r jma or jma (theta- jma) will be used for both junction-to-ambi ent on a 2s2p test board in natural convection and for junction-to-ambient with forc ed convection on both 1s and 2s2p test boards. it is anticipated that the generic name, theta-ja, will c ontinue to be commonly use d. the jedec standards can be consulted at http://www.jedec.org/ 8.4.2 estimation of junction temperature an estimation of the chip junction temper ature tj can be obtained from the equation t j = t a + (r ja x p d ) with t a = ambient temperature for the package in c r ? ja = junction to ambient thermal resistance in c/w p d = power dissipation in the package in w the junction to ambient thermal resistance is an industry standa rd value that provides a quick and easy estimation of thermal performance. unfortunately, there are two values in comm on usage: the value determined on a single layer board r ja and the value obtained on a four layer board r jma . actual application pcbs show a performance close to the simulated four layer board value although this may be somewhat degraded in case of signif icant power dissipated by other components placed close to the device. at a known board temperature, the junction temper ature tj is estimated using the following equation t j = t b + (r jb x p d ) with t b = board temperature at the package perimeter in c r jb = junction to board thermal resistance in c/w p d = power dissipation in the package in w when the heat loss from the package case to the air can be i gnored, acceptable predictions of junction temperature can be made. see thermal characteristics for more details on thermal management.
analog integrated circuit device data ? freescale semiconductor 152 mc34708 package mechanical dimensions 9 package mechanical dimensions the mc34708 is offered in two pin com patible 206 pin mapbga packages, an 8.0x8.0 mm, 0.5 mm pitch package, and a 13x13 mm, 0.8 mm pitch package. package dimensions are provided in package drawings. to find the most current package outline drawing, go to www.freescale.com and perform a keyword search for the drawing?s document number. dimensions shown are provided for reference only (for layout and design, refer to th e package outline drawing listed in the following figures). table 162. package drawing information package suffix package outline drawing number 206-pin mapbga (8 x 8), 0.5 mm vk 98asa00312d 206-pin mapbga (13 x 13), 0.8 mm vm 98asa00299d
analog integrated circuit device data ? 153 freescale semiconductor mc34708 package mechanical dimensions 9.1 206-pin mapbga (8 x 8), 0.5 mm vk suffix (pb-free) 206-pin 98asa00312d issue 0
analog integrated circuit device data ? freescale semiconductor 154 mc34708 package mechanical dimensions vk suffix (pb-free) 206-pin 98asa00312d issue 0
analog integrated circuit device data ? 155 freescale semiconductor mc34708 package mechanical dimensions 9.2 206-pin mapbga (13 x 13), 0.8 mm vm suffix (pb-free) 206-pin 98asa00299d issue a
analog integrated circuit device data ? freescale semiconductor 156 mc34708 package mechanical dimensions vm suffix (pb-free) 206-pin 98asa00299d issue a
analog integrated circuit device data ? 157 freescale semiconductor mc34708 reference section 10 reference section table 163. mc34708 reference documents reference description mc34708er errata
analog integrated circuit device data ? freescale semiconductor 158 mc34708 revision history 11 revision history . revision date description of changes 6.0 7/2011 ? initial release 7.0 10/2011 ? corrected the two pins sw2pwgd and sdwnb, and associated drawings. ? changed led driver electrical specifications , vpll matching from 3.0 to 4.0% ? changed vpll electrical specification , t on-vpll from 100 to 120 ? s ? changed swbst electrical specifications , i leak_swbst from 5.0 to 6.0 ? a ? added max limit to charger input current limit (using the usb input). ? added note (58) to v refddr ? changed r usb on value to 5.0 typ, 8.0 max ? set mic bias to 1.5 v, and changed on resistance values to 75 typ and 150 max. ? added efficiency values for all buck converter ? added diodes to the lx pin on sw1, sw2, sw3, sw4a, sw4b, and sw5. ? updated schematics to reflect the lx pin diodes on sw1, sw2, sw3, sw4a, sw4b, and sw5, and removed the 10 ? f vbusvin input capacitor. 8.0 7/2012 ? removed charger and coulomb counter functionality throughout the document. section 7.6 removed. ? updated figure 1 , figure 2 , figure 3 , figure 4 , figure 38 , figure 20 , figure 26 , figure 28 , figure 30 , figure 31 , figure 40 . ? update table 3 ? pin function changed to ?o? on pins vcore, vcoredig, valways, vcoreref, vddlp, and tsref. ? pin function to ?i? on pins adin11, tsx1/adin12, tsx2/adin13, tsy1/adin14 and tsy2/adin15 ? description for unsupported charger and coulomb counter pins modified. ? clarified ictest description ? update table 4 with maximum pin rating for all blocks . ? added table 7 ? die temp debounce settings? ? updated thermal monitor operation in section 5.2.1 ? removed pretmr, itrickle, vsrt and adc specifications in table 9 . ? changed typ current spec for on standby (lpm) from 260 ua to 340ua, changed on standby digital core from 370ua to 480ua and removed all charger conditions in table 10. ? updated section 6.1 feature list ? renamed all instances of apskip to aps. ? updated table 15: vsrtc quiescent current to 1.7ua @1.2v setting and 2.7ua @ 1.3v setting. ? glbrsttmr[1:0], value ?00? changed to invalid option in table 24 . ? removed interrupt, mask and sense bit related to charger and coulomb counter in table 21 . ? changed debounce time for thermxxx interrupts. ? updated sw4a/b operation and removed 3.3v setting from sw4a/b in section 7.5.4.6 ? removed aux attach in section 7.5.3.4 ? replaced ?under voltage detection? event in section 7.5.3.5 with ?bp lower than vbat_trkl? event. ? changed uvdet threshold to 3.1v (rising)/ 2.65v (falling) in table 27 ? added pwmps mode description on table 31 ? changed quiescent currents for all switching regulators iswxq in pwmps and aps modes. ? ldo short circuit protection feature no longer supported. ? changed adc channels 4 and 7 to ?reserved? ? added figure 19 ? removed vbattremth specification from table 77 ? added section 7.8.3 ? removed charger support from section 7.8.4 ? removed ivbus quiescent current specification for dedicated charger condition in table 97 ? updated components to bom in section 8.2 ? updated spi register map ? replaced figures 42-45 with table 104 spi/i2c register map ? updated table 101 and table 104 to match removed functionality ? updated table 105 through table 158 to match removed functionality
document number: mc34708 rev. 8.0 8/2012 information in this document is provided solely to enable system and software implementers to use freescale products. t here are no express or implied copyright licenses granted hereunder to design or fabric ate any integrated circuits based on the information in this document. freescale reserves the right to make changes without further notice to any products herein. freescale makes no warranty, representation, or guarantee regarding the suitability of its products for any particul ar purpose, nor does freescale assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including with out limitation consequential or incidental damages. ?typical? parameters that may be pr ovided in freescale data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. all operating parameters, including ?typicals,? must be validated for each customer application by customer?s te chnical experts. freescale does not convey any license under its patent rights nor the rights of others. freescale sells products pursuant to standard terms and conditions of sale, which can be found at the following address: store.esellerate.net/store/p olicy.aspx?selector=rt&s=str0326182960&pc. how to reach us: home page: freescale.com web support: freescale.com/support freescale, the freescale logo, altivec, c-5, codetest, codewarrior, coldfire, c- ware, energy efficient solutions logo, kinetis, mobilegt, po werquicc, processor expert, qoriq, qorivva, starcore, symphony, and vortiqa are trademarks of freescale semiconductor, inc., reg. u.s. pat. & tm. off. airfast, beekit, beestack, coldfire+, corenet, flexis, magniv, mxc, platform in a package, qoriq qonverge, quicc engine, ready play, safeassure, sm artmos, turbolink, vybrid, and xtrinsic are trademarks of freescale semiconductor, inc. all other produc t or service names are the property of thei r respective owners. ? ? 2012 freescale semiconductor, inc.

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